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参数资料
| 型号： | TAS5086DBTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
| 封装： | GREEN, TSSOP-38 |
| 文件页数： | 20/47页 |
| 文件大小： | 814K |
| 代理商： | TAS5086DBTG4 |
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CLOCK CONTROL REGISTER (0x00)
www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Default values are in bold, table values "X" equals don't care and table values "–" equals an expansion of the table for
detailed description of the respective bit.
NO. OF
SUBADDRESS
REGISTER NAME
CONTENTS
INITIALIZATION VALUE
BYTES
0x25
PWM MUX register
Description shown in subsequent section
0x00, 0x32, 0x45, 0x10
0x26
1/G register
4
x[25:24] x[23:16], x[15:8], x[7:0]
0x00, 0x80, 0x00, 0x00
0x27
RESERVED(1)
0x28
Scale register
4
x[25:24] x[23:16], x[15:8], x[7:0]
0x00, 0x80, 0x00, 0x00
0x29–0xFD
RESERVED(1)
0xFE
Repeat subaddress
4+4N
0x00, 0x00, 0x00, 0x00
0xFF
RESERVED(1)
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates, based on the sample rate and associated clock frequencies. In the autodetect mode, the clocks
are determined automatically by the TAS5086. In this case, the clock control register contains the autodetected
clock status as automatically detected. Bits D7–D5 select the sample rate. Bits D4–D2 select the MCLK
frequency. Bit D1 selects the bit clock (SCLK) frequency. Bit D0 is used in manual mode only. In this mode,
when the clocks are updated, a 1 must be written to D1 to inform the TAS5086 that the written clocks are valid.
Table 2. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
–
fS = 32-kHz sample rate
0
1
–
fS = 38-kHz sample rate
0
1
0
–
fS = 44.1-kHz sample rate
0
1
–
fS = 48-kHz sample rate
1
0
–
fS = 88.2- kHz sample rate
1
0
1
–
fS = 96-kHz sample rate
1
0
–
fS = 176.4-kHz sample rate
1
–
fS = 192-kHz sample rate
–
0
–
MCLK frequency = 64 × fS
(1)
–
0
1
–
MCLK frequency = 128 × fS
–
0
1
0
–
MCLK frequency = 192 × fS
–
0
1
–
MCLK frequency = 256 × fS
–
1
0
–
MCLK frequency = 384 × fS
–
1
0
1
–
MCLK frequency = 512 × fS
–
1
0
–
Reserved
–
1
–
Reserved
–
1
–
Bit clock (SCLK) frequency = 48 × fS
–
0
–
Bit clock (SCLK) frequency = 64 × fS
–
0
Clock not valid (in manual mode only)
–
1
Clock valid (in manual mode only)
(1)
MCLK frequency = 64 x fS is not available for 32-, 44.1-, 48-, 88.2-, and 96-kHz data rates
Copyright 2005–2008, Texas Instruments Incorporated
27
Product Folder Link(s): TAS5086
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