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参数资料
| 型号： | TAS5103DAPRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 15 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO32 |
| 封装： | GREEN, PLASTIC, HTSSOP-32 |
| 文件页数： | 9/25页 |
| 文件大小： | 1335K |
| 代理商： | TAS5103DAPRG4 |
THEORY OF OPERATION
POWER SUPPLIES
INTEGRATED GATE DRIVE SUPPLY (GVDD)
SYSTEM POWER-UP/POWER-DOWN
Powering Up
www.ti.com .............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a 100-nF
ceramic capacitor placed as close as possible to
To facilitate system design, the TAS5102/3 needs
each supply pin. It is recommended to follow the PCB
only a 3.3-V supply in addition to the (typical) 18-V
layout of the TAS5102/3 reference design. For
power-stage supply. An internal voltage regulator
additional information on recommended power supply
provides suitable voltage levels for the gate drive
and
required
components,
see
the
application
circuitry. Additionally, all circuitry requiring a floating
diagrams given previously in this data sheet.
voltage supply, e.g., the high-side gate drive, is
The 3.3-V supply should be from a low-noise,
accommodated by built-in bootstrap circuitry requiring
low-output-impedance voltage regulator. Likewise, the
only a few external capacitors.
18-V power-stage supply is assumed to have low
In
order
to
provide
outstanding
electrical
and
output impedance and low noise. The power-supply
acoustical characteristics, the PWM signal path for
sequence is not critical as facilitated by the internal
the
output
stage
is
designed
as
identical,
power-on-reset circuit. Moreover, the TAS5102/3 is
independent half-bridges. For this reason, each
fully protected against erroneous power-stage turnon
half-bridge has separate bootstrap pins (BST_X), and
due to parasitic gate charging.
power-stage supply pins (PVDD_X). The gate drive
voltages (GVDD_AB and GVDD_CD) are derived
from the PVDD voltage. Separate, internal voltage
regulators reduce and regulate the PVDD voltage to a
The TAS5103 has an integrated gate drive supply,
voltage appropriate for efficient gave drive operation.
which eliminates the need for an external regulator. If
Furthermore, an additional pin (VREG) is provided as
the PVDD is 12 V (i.e., max PVDD < 13.2 V), it is
supply for all common logic circuits. Special attention
possible to connect the PVDD to the GVDD through a
should be paid to placing all decoupling capacitors as
ten ohm resistor. This will allow the power stage to
close to their associated pins as possible. In general,
operate as low a 7 V during dips. Otherwise the
inductance between the power supply pins and
GVDD undervoltage protection will shutdown the
decoupling
capacitors
must
be
avoided.
(See
outputs when the supply drops to 8 V. Care must be
reference
board
documentation
for
additional
taken to not connect GVDD and PVDD together in
information.)
this manner if the operating voltage is higher than
12 V.
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
SEQUENCE
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive power--
supply pin (GVDD_X) and the bootstrap pin. When
The
outputs
of
the
H-bridges
remain
in
a
the
power-stage
output
is
high,
the
bootstrap
high-impedance state until the internal gate-drive
capacitor
potential
is
shifted
above
the
output
supply voltage (GVDD_XY) and external VREG
potential and thus provides a suitable voltage supply
voltages are above the undervoltage protection (UVP)
for the high-side gate driver. In an application with
voltage threshold (see the Electrical Characteristics
PWM switching frequencies in the range from 352
section of this data sheet). Although not specifically
kHz to 384 kHz, it is recommended to use 33-nF
required, it is recommended to hold RESET in a low
ceramic capacitors, size 0603 or 0805, for the
state while powering up the device. This allows an
bootstrap supply. These 33-nF capacitors ensure
internal circuit to charge the external bootstrap
sufficient energy storage, even during minimal PWM
capacitors by enabling a weak pulldown of the
duty cycles, to keep the high-side power stage FET
half-bridge
output.
The
output
impedance
is
(LDMOS) fully turned on during the remaining part of
approximately 3K
under this condition, unless mode
the PWM cycle. In an application running at a
1, 0 (Single-ended Mode), is used. This means that
reduced switching frequency, generally 192 kHz, the
the TAS5102/3 should be held in reset for at least
bootstrap capacitor might need to be increased in
200
S to ensure that the bootstrap capacitors are
value.
charged. This also assumes that the recommended
0.033-
F bootstrap capacitors are used. Changes to
Special attention should be paid to the power-stage
bootstrap capacitor values will change the bootstrap
power supply; this includes component selection,
capacitor charge time. To avoid pops and clicks,
PCB placement, and routing. As indicated, each
follow the recommended timing diagram in Figure 20.
half-bridge has independent power-stage supply pins
(PVDD_X). For optimal electrical performance, EMI
Copyright 2008, Texas Instruments Incorporated
17
Product Folder Link(s): TAS5102 TAS5103
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