参数资料
型号: TC3401EPE
元件分类: ADC
英文描述: 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP16
封装: PLASTIC, DIP-16
文件页数: 7/12页
文件大小: 70K
代理商: TC3401EPE
4
16-BIT LOW COST, LOW POWER
A/D CONVERTER
TC3401
TC3401- 1
10/14/99
PIN DESCRIPTION
TC3401
Pin No.
Symbol
Description
1, 3
INn
+
Analog Input. This is the positive terminal of a true differential input consisting of INn
+
and INn
. V
IN(n) = (INn
+ – INn).
2, 4
INn
Analog Input. This is the negative terminal of a true differential input consisting of INn
+ and
INn
. V
IN(n) = (INn
+ – INn) INncan swing to, but not below, ground.
5
PFI
Analog Input. This is the positive input to an internal comparator used as a threshold
detector. The negative input is tied to an internal reference.
6VTH
Analog Input. This is the positive input to the internal comparator used to monitor the
voltage supply. The negative input is tied to an internal reference. When VTH falls below
the internal reference, the reset generator drives RESET low as specified in the
Electrical
Characteristics section.
7
REFIN
Analog Input. The converter’s reference voltage is the differential between this pin and
ground times two. It may be tied directly to REFOUT or scaled using a resistor divider. Any
user supplied reference voltage or the power supply rail may be used in place of REFOUT.
8
GND
Ground Terminal.
9
REFOUT
Analog Output. The internal reference connects to this pin. It may be scaled externally, if
desired, and tied to the REFIN input to provide the converter’s reference voltage. Care
must be taken in connecting external circuitry to this pin. This pin is in a high impedance
state during sleep mode.
10
SDAT
Digital Output (push-pull). This is the MicroPort serial data output. SDAT is driven low
while the TC3401 is converting data, effectively providing a “busy” signal. After the
conversion is complete, every high-to-low transition on the SCLK pin puts a bit from the
resulting data word on the SDAT pin (fromMSB to LSB).
11
PFO
Digital Output (open drain). This is the output of the internal threshold detector. When PFI
is less than the internal reference, PFO is driven low.
12
ENABLE
Digital Input. When this input control is pulled low, the part is internally restarted. That is,
any data conversion or data read sequence is cleared and the part goes into sleep mode.
When ENABLE returns high, the part resumes normal operation.
13
RESET
Digital Output (open drain). This is the output of the VDD monitor reset generator. RESET
is driven low when a power-on reset or brown-out condition is detected. (See
AC Electrical
Characteristics.)
14
ADDR
Digital Input. This input controls the analog input multiplexer to select one of two input
channels. This address is latched at the falling edge of the SCLK, which starts an A/D
conversion. 0 = Input 1, 1 = Input 2.
15
SCLK
Digital Input. This is the MicroPort serial clock input.The TC3401 comes out of sleep
mode and a conversion cycle begins when this pin is driven low. After the conversion
starts, each additional falling edge (up to six) detected on SCLK for t4 seconds reduces
the A/D resolution by one bit. When the conversion is complete, the data word can be
shifted out on the SDAT pin by clocking the SCLK pin.
16
VDD
Power Supply Input.
相关PDF资料
PDF描述
TC3401EQR 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
TC3401VPE 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP16
TC3401VQR 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
TC3401VQRRT 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
TC3401VQRTR 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
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