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参数资料
| 型号： | TC35273 |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA201 |
| 封装： | 15 X 15 MM, PLASTIC, FBGA-201 |
| 文件页数： | 2/23页 |
| 文件大小： | 237K |
| 代理商： | TC35273 |
MPEG-4 Audiovisual Codec LSI
Preliminary
TC35273
TOSHIBA Confidential
2000-4-27
10/23
Version 0.90
3. Interface Specifications
3.1 Host Interface
An external host CPU accesses to TC35273 via a host interface. The access timing of a read, a
write, and an interrupt operation are explained below. The host interface has two access modes; a
handshake access mode and a synchronized access mode.
3.1.1 Handshake access mode
In this mode, the host CPU has to finish an access operation after a waiting signal (/HWAIT)
becomes high.
Fig.3 shows the timing diagram of a read operation. A read access starts by asserting both a chip
select signal (/HCS) and a read signal (/RD) (timing (a)). At this timing, /HWAIT becomes low. When
the read data are ready, /HWAIT becomes high (timing (b)). The host CPU gets the read data and
finishes the read operation by negating both /HCS and /HRD (timing (c)).
Fig.4 shows the timing diagram of a write operation. A write access starts by asserting both /HCS
and a write signal (/WR) (timing (a)). At this timing, /HWAIT becomes low. When TC35273 gets the
write data, /HWAIT becomes high (timing (b)). After that, the host CPU finishes the write operation by
negating both /HCS and /HWR (timing (c)).
Fig. 3 Read Operation in handshake mode
HADDR
/HRD
HDAT
/HWAIT
/HCS
T
CSS
T
WTAD
T
DTOD
T
DTVD
T
DTRS
T
DTID
T
RDH
T
RR
T
ADH
T
WTID
T
ADS
T
CSH
(a)
(b)
(c)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TC35274 | 制造商:TOSHIBA 制造商全称:Toshiba Semiconductor 功能描述:TOSHIBA MPEG-4 Video Decoder LSI |
| TC3531 | 制造商:TRANSCOM 制造商全称:TRANSCOM 功能描述:5.8 GHz 1W MMIC |
| TC3532 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4.9 - 6 GHz 29dBm MMIC |
| TC35321 | 制造商:General Electric Company 功能描述:30A 3P DBL THR SS N1 240V NONFUSE |
| TC3538 | 制造商:TRANSCOM 制造商全称:TRANSCOM 功能描述:5 - 6 GHz 1W MMIC |
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