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参数资料
| 型号： | TC534CPL |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 26/28页 |
| 文件大小： | 568K |
| 代理商： | TC534CPL |
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2007 Microchip Technology Inc.
DS21433C-page 7
TC530/TC534
16
23
20
DOUT
Logic Level Output. Serial port data output pin. This pin is
enabled only when R/W is high.
17
24
21
DCLK
Logic Input, Positive and Negative Edge Triggered. Serial
port clock. When R/W is high, serial data is clocked out of
the TC530/TC534A (on DOUT) at each high-to-low transition
of DCLK. A/D initialization data (LOAD VALUE) is clocked
into the TC530/TC534 (on DIN) at each low-to-high
transition of DCLK. A maximum serial port DCLK frequency
of 3 MHz is permitted.
18
25
22
DIN
Logic Level Input. Serial port input pin. The A/D converter
integration time (TINT) and Auto Zero time (TAZ) values are
determined by the LOAD VALUE byte clocked into this pin.
This initialization must take place at power up, and can be
rewritten (or modified and rewritten) at any time. The LOAD
VALUE is clocked into DIN MSB first.
19
26
23
R/W
Logic Level Input. This pin must be brought low to perform a
write to the serial port (e.g. initialize the A/D converter). The
DOUT pin of the serial port is enabled only when this pin is
high.
20
27
24
EOC
Open Drain Output. End-of-Conversion (EOC) is asserted
any time the TC530/TC534 is in the AZ phase of
conversion. This occurs when either the TC530/TC534
initiates a normal AZ phase or when RESET is pulled high.
EOC is returned high when the TC530/TC534 exits AZ.
Since EOC is driven low immediately following completion
of a conversion cycle, it can be used as a DATA READY
processor interrupt.
21
30
28
RESET
Logic Level Input. It is necessary to force the TC530/TC534
into the Auto Zero phase when power is initially applied.
This is accomplished by momentarily taking RESET high.
Using an I/O port line from the microprocessor or by
applying an external system reset signal or by connecting a
0.01 F capacitor from the RESET input to VDD. Conver-
sions are performed continuously as long as RESET is low
and conversion is halted when RESET is high. RESET may
therefore be used in a complex system to momentarily
suspend conversion (for example, while the address lines
of an input multiplexer are changing state). In this case,
RESET should be pulled high only when the EOC is LOW
to avoid excessively long integrator discharge times which
could result in erroneous conversion. (See Applications
Section).
22
32
30
VCCD
Analog Input. Power supply connection for digital logic and
serial port. Proper power-up sequencing is critical, see the
Applications section.
23
34
32
OSC
Input. The negative power supply converter normally runs
at a frequency of 100 kHz. This frequency can be slowed
down to reduce quiescent current by connecting an external
capacitor between this pin and V+DD.
See Section 2.0 “Typical Performance Curves”, Typical
Characteristics.
25
37
35
VDD
Analog Input. Power supply connection for the A/D analog
section and DC-DC converter. Proper power-up sequencing
is critical, (See the Applications section).
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
(TC530)
28-Pin PDIP
Pin Number
(TC530)
28-Pin SOIC
Pin Number
(TC534)
40-Pin PDIP
Pin
Number
(TC534)
44-Pin
MQFP
Sym
Description
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