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参数资料
| 型号： | TC534CPL |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 8/28页 |
| 文件大小： | 568K |
| 代理商： | TC534CPL |
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TC530/TC534
DS21433C-page 16
2007 Microchip Technology Inc.
6.4
Data Read Cycle
Data is shifted out of the serial port in the following
order: End of Conversion (EOC), Overrange (OVR),
Polarity (POL), conversion data (MSB first). When R/W
is high, the state of the EOC bit can be polled by simply
reading the state of DOUT. This allows the processor to
determine if new data is available without connecting
an additional wire to the EOC output pin (this is
especially useful in a polled environment). Refer to
FIGURE 6-1:
Serial Port Data Read
Cycle.
6.5
Load Value Write Cycle
Following the power-up reset pulse, the LOAD VALUE
(which sets the duration of AZ and INT) must next be
transmitted to the serial port. To accomplish this, the
processor monitors the state of EOC (which is available
as a hardware output or at DOUT). R/W is taken low to
initiate the write cycle only when EOC is low (during the
AZ phase). (Failure to observe EOC low may cause an
offset voltage to be developed across CINT, resulting in
erroneous readings). The 8-bit LOAD VALUE data on
DIN is clocked in by DCLK. The processor then
terminates the write cycle by taking R/W high. (Data is
transferred from the serial input shift register to the time
base counter on the rising edge of R/W and data
conversion is initiated). See Figure 6-2.
6.6
Input Multiplexer (TC534 Only)
A 4-input, differential multiplexer is included in the
TC534. The states of channel address lines A0 and A1
determine which differential VIN pair is routed to the
converter input. A0 is the least significant address bit
(i.e., channel 1 is selected when A0 = 0 and A1 = 0).
The multiplexer is designed to be operated in a differ-
ential mode. For single-ended inputs, the CHx- input for
the channel under selection must be connected to the
ground reference associated with the input signal.
6.7
DC/DC Converter
An on-board, TC7660H-type charge pump supplies
negative bias to the converter circuitry, as well as to
external devices. The charge pump develops a
negative output voltage by moving charge from the
power supply to the reservoir capacitor at VSS by way
of the commutating capacitor connected to the CAP+
and CAP- inputs.
The charge pump clock operates at a typical frequency
of 100 kHz. If lower quiescent current is desired, the
charge pump clock can be slowed by connecting an
external capacitor from the OSC pin to VDD. Reference
typical characteristics curves.
FIGURE 6-2:
TC530/TC534 Initialization and Load Value Write Cycle.
EOC OVR POL MSB
LSB
R/W
DCLK
DOUT
EOC
R/W
RESET
DCLK
DIN
1
00
11
1
AZ
LOAD VALUE
MSB
LSB
INT
DINT
IZ
AZ...
Conversion
Phase
Timing
Status
Converter held in AZ
state due to RESET =
1
Write LOAD VALUE to Serial Port
Power-up RESET
Undefined
Converter in Normal Service
R/W brought LOW during AZ
for serial port write cycle
R/W = HIGH strobes
LOAD VALUE into
timebase and starts
conversion
Continuous Conversions
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