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| 型号： | TC654EUNTR |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, PDSO10 |
| 封装： | PLASTIC, MSOP-10 |
| 文件页数： | 7/36页 |
| 文件大小： | 706K |
| 代理商： | TC654EUNTR |
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2002 Microchip Technology Inc.
DS21734A-page 15
TC654/TC655
5.0
SERIAL COMMUNICATION
5.1
SMBus 2-Wire Interface
The Serial Clock Input (SCLK) and the bi-directional
data port (SDA) form a 2-wire bi-directional serial port
for communicating with the TC654/TC655. The follow-
ing bus protocols have been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following Serial Bus conventions have
been defined.
TABLE 5-1:
TC654/TC655 SERIAL BUS
CONVENTIONS
5.1.1
DATA TRANSFER
The TC654/TC655 support a bi-directional 2-Wire bus
and data transmission protocol. The serial protocol
sequencing is illustrated in Figure 1-1. Data transfers
are initiated by a start condition (START), followed by a
device address byte and one or more data bytes. The
device address byte includes a Read/Write selection
bit. Each access must be terminated by a Stop Condi-
tion (STOP). A convention call Acknowledge (ACK)
confirms the receipt of each byte. Note that SDA can
only change during periods when SCLK is LOW (SDA
changes while SCLK is HIGH are reserved for Start
and Stop conditions). All bytes are transferred MSB
(most significant bit) first.
5.1.2
MASTER/SLAVE
The device that sends data onto the bus is the transmit-
ter and the device receiving data is the receiver. The
bus is controlled by a master device which generates
the serial clock (SCLK), controls the bus access and
generates the START and STOP conditions. The
TC654/TC655 always work as a slave device. Both
master and slave devices can operate as either trans-
mitter or receiver, but the master device determines
which mode is activated.
5.1.3
START CONDITION (START)
A HIGH to LOW transition of the SDA line while the
clock (SCLK) is HIGH determines a START condition.
All commands must be preceded by a START
condition.
5.1.4
ADDRESS BYTE
Immediately following the Start Condition, the host
must transmit the address byte to the TC654/TC655.
The 7-bit SMBus address for the TC654/TC655 is
0011 011
. The 7-bit address transmitted in the serial
bit stream must match for the TC654/TC655 to respond
with an Acknowledge (indicating the TC654/TC655 is
on the bus and ready to accept data). The eighth bit in
the Address Byte is a Read-Write Bit. This bit is a ‘1’ for
a read operation or ‘0’ for a write operation. During the
first phase of any transfer, this bit will be set = 0 to indi-
cate that the command byte is being written.
5.1.5
STOP CONDITION (STOP)
A LOW to HIGH transition of the SDA line while the
clock (SCLK) is HIGH determines a STOP condition.
All operations must be ended with a STOP condition.
5.1.6
DATA VALID
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
Term
Description
Transmitter
The device sending data to the bus.
Receiver
The device receiving data from the
bus.
Master
The device which controls the bus: ini-
tiating transfers (START), generating
the clock and terminating transfers
(STOP).
Slave
The device addressed by the master.
Start
A unique condition signaling the
beginning of a transfer indicated by
SDA falling (High to Low) while SCLK
is high.
Stop
A unique condition signaling the end
of a transfer indicated by SDA rising
(Low to High) while SCLK is high.
ACK
A Receiver acknowledges the receipt
of each byte with this unique condi-
tion. The Receiver pulls SDA low dur-
ing SCLK high of the ACK clock-pulse.
The Master provides the clock pulse
for the ACK cycle.
Busy
Communication is not possible
because the bus is in use.
NOT Busy
When the bus is idle, both SDA and
SCLK will remain high.
Data Valid
The state of SDA must remain stable
during the high period of SCLK in
order for a data bit to be considered
valid. SDA only changes state while
SCLK is low during normal data trans-
fers. (See START and STOP condi-
tions)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TC655 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Dual SMBus⑩ PWM Fan Speed Controllers With Fan Fault Detection |
| TC655EUN | 功能描述:软开关 PWM 控制器 Dual RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| TC655EUNTR | 功能描述:软开关 PWM 控制器 Dual RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| TC65A | 制造商:CDE 制造商全称:Cornell Dubilier Electronics 功能描述:Axial Leaded Aluminum Electrolytic Capacitors |
| TC65I | 制造商:CINTERION 功能描述:MODULE GSM/GPRS QUADBAND + JAVA TC65I 制造商:CINTERION 功能描述:MOD, GSM / GPRS, QUAD BAND, TCP/IP 制造商:CINTERION 功能描述:MOD, GSM / GPRS, QUAD BAND, I2C, SPI, USB, TCP/IP; No. of Channels:4; Supply Voltage Min:3.2V; Supply Voltage Max:4.5V; Frequency RF:1900MHz; Module Interface:I2C, SPI, USB; RF Coax Type:1.9 GHz; Supply Voltage Range:3.2V to 4.5V ;RoHS Compliant: Yes |
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