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| 型号： | TC7126CLW713 |
| 厂商： | Microchip Technology |
| 文件页数： | 10/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 3 1/2DGT LCD DVR 44-PLCC |
| 标准包装： | 500 |
| 显示器类型： | LCD |
| 配置： | 7 段显示 |
| 数字或字符： | A/D，3.5 位数字 |
| 电流 - 电源： | 55µA |
| 电源电压： | 9V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 带卷 (TR) |
TC7126/A
4.0
ANALOG SECTION
The differential input voltage must be within the device
Common mode range when the converter and mea-
In addition to the basic integrate and de-integrate dual
slope cycles discussed above, the TC7126A design
incorporates an auto-zero cycle. This cycle removes
buffer amplifier, integrator and comparator offset volt-
age error terms from the conversion. A true digital zero
reading results without external adjusting potentiome-
ters. A complete conversion consists of three phases:
sured system share the same power supply common
(ground). If the converter and measured system do not
share the same power supply common, V IN - should be
tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that
signals less than 1LSB are correctly determined. This
1.
2.
3.
4.1
Auto-Zero phase
Signal Integrate phase
Reference Integrate phase
Auto-Zero Phase
allows precision null detection limited only by device
noise and auto-zero residual offsets.
4.3
Reference Integrate Phase
The third phase is reference integrate or de-integrate.
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero input condition.
Additional analog gates close a feedback loop around
the integrator and comparator. This loop permits com-
parator offset voltage error compensation. The voltage
level established on C AZ compensates for device offset
voltages. The auto-zero phase residual is typically
10 μ V to 15 μ V. The auto-zero cycle length is 1000 to
3000 clock periods.
4.2 Signal Integrate Phase
The auto-zero loop is entered and the internal differen-
tial inputs connect to V IN + and V IN -. The differential
input signal is integrated for a fixed time period. The
TC7126/A signal integration period is 1000 clock
periods or counts. The externally set clock frequency is
divided by four before clocking the internal counters.
The integration time period is:
EQUATION 4-1:
V IN - is internally connected to analog common and
V IN + is connected across the previously charged refer-
ence capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity
to cause the integrator output to return to zero. The
time required for the output to return to zero is propor-
tional to the input signal and is between 0 and 2000
counts. The digital reading displayed is:
EQUATION 4-2:
V IN
1000 V REF
T SI =
4
F OSC
x 1000
Where: F OSC = external clock frequency.
DS21458C-page 10
? 2006 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TC7126CPL | 功能描述:LCD 驱动器 Low Power RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| TC7126CPL | 制造商:Microchip Technology Inc 功能描述:3.5 DIGIT ADC CMOS 7126 DIP40 制造商:Microchip Technology Inc 功能描述:3.5 DIGIT ADC, CMOS, 7126, DIP40 制造商:Microchip Technology Inc 功能描述:3.5 DIGIT ADC, CMOS, 7126, DIP40; Resolution (Bits):3.5bit; Supply Voltage Max:15V; Supply Current:55A; Digital IC Case Style:DIP; No. of Pins:40; Input Channel Type:Differential; Data Interface:Parallel; Operating Temperature ;RoHS Compliant: Yes |
| TC7126IPL | 功能描述:LCD 驱动器 Low Power RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| TC7126RCPL | 功能描述:LCD 驱动器 Low Power RoHS:否 制造商:Maxim Integrated 数位数量:4.5 片段数量:30 最大时钟频率:19 KHz 工作电源电压:3 V to 3.6 V 最大工作温度:+ 85 C 最小工作温度:- 20 C 封装 / 箱体:PDIP-40 封装:Tube |
| TC7126RIPL | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:3-1/2 Digit Analog-to-Digital Converters |
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