参数资料
型号: TC7126CLW713
厂商: Microchip Technology
文件页数: 12/26页
文件大小: 0K
描述: IC ADC 3 1/2DGT LCD DVR 44-PLCC
标准包装: 500
显示器类型: LCD
配置: 7 段显示
数字或字符: A/D,3.5 位数字
电流 - 电源: 55µA
电源电压: 9V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC
包装: 带卷 (TR)
TC7126/A
6.0
COMPONENT VALUE
6.4
Integrating Resistor (R INT )
SELECTION
6.1 Auto-Zero Capacitor (C AZ )
The C AZ capacitor size has some influence on system
noise. A 0.47 μ F capacitor is recommended for 200mV
full scale applications where 1LSB is 100 μ V. A 0.033 μ F
capacitor is adequate for 2.0V full scale applications. A
mylar type dielectric capacitor is adequate.
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling
current is 6 μ A. The integrator and buffer can supply
1 μ A drive current with negligible linearity errors. R INT is
chosen to remain in the output stage linear drive
region, but not so large that PC board leakage currents
induce errors. For a 200mV full scale, R INT is 180k Ω . A
2V full scale requires 1.8M Ω .
6.2
Reference Voltage Capacitor (C REF )
Component
Value
Nominal Full Scale Voltage
200mV 2V
The reference voltage, used to ramp the integrator out-
put voltage back to zero during the reference integrate
phase, is stored on C REF . A 0.1 μ F capacitor is accept-
able when V REF - is tied to analog common. If a large
C AZ
R INT
C INT
0.33 μ F
180k Ω
0.047 μ F
0.033 μ F
1.8M Ω
0.047 μ F
Common mode voltage exists (V REF - – analog com-
mon) and the application requires a 200mV full scale,
increase C REF to 1 μ F. Rollover error will be held to less
than 0.5 count. A Mylar type dielectric capacitor is
Note:
6.5
F OSC = 48kHz (3 readings per sec).
Oscillator Components
adequate.
C OSC should be 50pF; R OSC is selected from the
equation:
6.3
Integrating Capacitor (C INT )
C INT should be selected to maximize integrator output
EQUATION 6-2:
voltage swing without causing output saturation. Due to
the TC7126A’s superior analog common temperature
coefficient specification, analog common will normally
F OSC =
0.45
RC
supply the differential voltage reference. For this case,
a ±2V full scale integrator output swing is satisfactory.
For 3 readings per second (F OSC = 48kHz), a 0.047 μ F
value is suggested. For 1 reading per second, 0.15 μ F
is recommended. If a different oscillator frequency is
used, C INT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
An exact expression for C INT is:
EQUATION 6-1:
For a 48kHz clock (3 conversions per second),
R = 180k Ω .
Note that F OSC is 44 to generate the TC7126A’s
internal clock. The backplane drive signal is derived by
dividing F OSC by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal integrate period should be a multiple of
60Hz. Oscillator frequencies of 24kHz, 12kHz, 80kHz,
60kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion, oscillator frequencies of 20kHz, 100kHz,
Where:
C INT =
? 1 ? ? V FS ?
(4000) ? F OSC ? ? R INT ?
V INT
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
F OSC =
V FS =
R INT =
V INT =
Clock frequency at Pin 38
Full scale input voltage
Integrating resistor
Desired full scale integrator output swing
At 3 readings per second, a 750 Ω resistor should be
placed in series with C INT . This increases accuracy by
compensating for comparator delay. C INT must have
low dielectric absorption to minimize rollover error. A
polypropylene capacitor is recommended.
DS21458C-page 12
? 2006 Microchip Technology Inc.
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