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| 型号： | TC7135CBURT |
| 元件分类： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 13/16页 |
| 文件大小： | 217K |
| 代理商： | TC7135CBURT |
6
TC7135
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135-10 9/27/99
Table 1. Internal Analog Gate Status
Conversion
Reference
Cycle Phase
SWI
SWRI
+
SWRI
–
SWZ
SWR
SW1
SWIZ
Schematic
System Zero
Closed
3B
Input Signal
Closed
3C
Integration
Reference Voltage
Closed*
Closed
3D
Integration
Integrator
Closed
3E
Output Zero
*NOTE: Assumes a positive polarity input signal. SWRI
– would be closed for a negative input signal.
Internal Analog Gate Status
System Zero Phase
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by charg-
ing CAZ (auto-zero capacitor) with a compensating error
voltage. With zero input voltage, the integrator output re-
mains at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The refer-
ence capacitor charges to the reference voltage potential
through SWR. A feedback loop, closed around the integrator
and comparator, charges the CAZ with a voltage to compen-
sate for buffer amplifier, integrator, and comparator offset
voltages. (See Figure 3B.)
Analog Input Signal Integration Phase
The TC7135 integrates the differential voltage between
the +INPUT and –INPUT. The differential voltage must be
within the device's common-mode range; –1V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase. (See Figure 3C.)
Reference Voltage Integration Phase
The previously-charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero. (See Figure 3D.) The digital reading
displayed is:
Reading = 10,000
.
Integrator Output Zero Phase
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
condition exists, the phase is extended to 6200 clock cycles.
(See Figure 3E.)
Differential Input
VREF
Analog Section Functional Description
Differential Inputs
The TC7135 operates with differential voltages (+IN-
PUT, pin 10 and –INPUT, pin 9) within the input amplifier
common-mode range which extends from 1V below the
positive supply to 1V above the negative supply. Within this
common-mode voltage range, an 86dB common-mode
rejection ratio is typical.
The integrator output also follows the common-mode
voltage and must not be allowed to saturate. A worst-case
condition exists, for example, when a large positive com-
mon-mode voltage with a near full-scale negative differential
input voltage is applied. The negative input signal drives the
integrator positive when most of its swing has been used up
by the positive common-mode voltage. For these critical
applications, the integrator swing can be reduced to less
than the recommended 4V full-scale swing, with some loss
of accuracy. The integrator output can swing within 0.3V of
either supply without loss of linearity.
Analog Common
ANALOG COMMON (pin 3) is used as the – INPUT
return during the auto-zero and deintegrate phases. If
–INPUT is different from analog common, a common-mode
voltage exists in the system. This signal is rejected by the
excellent CMRR of the converter. In most applications,
–INPUT will be set at a fixed known voltage (power supply
common, for instance). In this application, analog common
should be tied to the same point, thus removing the common-
mode voltage from the converter. The reference voltage is
referenced to analog common.
Reference Voltage
The reference voltage input (REF IN, pin 2) must be a
positive voltage with respect to analog common. Two refer-
ence voltage circuits are shown in Figure 5.
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