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| 型号： | TC7135CLI |
| 厂商： | Microchip Technology |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 4 1/2DGT 28-PLCC |
| 标准包装： | 39 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | BCD |
| 数字或字符： | A/D，4.5 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 4 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC |
| 包装： | 管件 |
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TC7135
TABLE 6-2:
LINE FREQUENCY
resistor (a few tens of ohms in the recommended
REJECTION VS. CLOCK
FREQUENCY
Line Frequency
Oscillator Frequency
Rejection
(kHz)
(Hz)
circuit), the comparator delay can be compensated and
the maximum clock frequency extended by
approximately a factor of 3. At higher frequencies,
ringing and second-order breaks will cause significant
nonlinearities in the first few counts of the instrument.
The minimum clock frequency is established by
300
200
150
120
100
40
33-1/3
250
60
50
leakage on the auto-zero and reference capacitors.
With most devices, measurement cycles as long as 10
seconds give no measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0 “Typical Applications” . The
multiplexed output means that if the display takes
significant current from the logic supply, the clock
should have good PSRR.
166-2/3
125
6.4
Zero Crossing Flip Flop
100
100
50, 60,400
The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half clock pulse have died down. False zero crossings
The conversion rate is easily calculated:
EQUATION 6-3:
Clock Frequency (Hz)
Reading 1/sec = ----------------------------------------------------
4000
caused by clock pulses are not recognized. Of course,
the flip flop delays the true zero crossing by up to one
count in every instance. If a correction were not made,
the display would always be one count too high.
Therefore, the counter is disabled for one clock pulse at
the beginning of the reference integrate (de-integrate)
phase. This one-count delay compensates for the delay
of the zero crossing flip flop and allows the correct
6.3
High-Speed Operation
number to be latched into the display. Similarly, a one-
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3 μs delay, at a clock frequency
count delay at the beginning of auto-zero gives an
overload display of 0000 instead of 0001. No delay
occurs during signal integrate so that true ratiometric
readings result.
of 160 kHz (6 μs period). Half of the first reference inte-
grate clock period is lost in delay. This means that the
6.5
Generating a Negative Supply
meter reading will change from 0 to 1 with a 50 μV
input, 1 to 2 with 150 μV, 2 to 3 at 250 μV, etc. This tran-
sition at midpoint is considered desirable by most
users. However, if the clock frequency is increased
appreciably above 200 kHz, the instrument will flash
A negative voltage can be generated from the positive
supply by using a TC7135 (see Figure 6-1 ).
+5V
"1" on noise peaks, even when the input is shorted.
For many dedicated applications where the input signal
V+
11
8
is always of one polarity, the delay of the comparator
need not be a limitation. Since the nonlinearity and
noise do not increase substantially with frequency, clock
rates of up to ~1 MHz may be used. For a fixed clock
frequency, the extra count (or counts) caused by
comparator delay will be a constant and can be
subtracted out digitally.
TC7135
V–
24
1
(-5V)
10 μF
+
5
4
TC7660
2
+
10 μF
3
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value
resistor in series with the integrating capacitor. The
effect of the resistor is to introduce a small pedestal
voltage on to the integrator output at the beginning of
the reference integrate phase. By careful selection of
the ratio between this resistor and the integrating
? 2007 Microchip Technology Inc.
FIGURE 6-1:
Generator.
Negative Supply Voltage
DS21460D-page 13
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