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参数资料
型号： TC7135CLI
厂商： Microchip Technology
文件页数： 7/28页
文件大小： 0K
描述： IC ADC 4 1/2DGT 28-PLCC
标准包装： 39
显示器类型： LED
配置： 7 段显示
接口： BCD
数字或字符： A/D，4.5 位数字
电流 - 电源： 1mA
电源电压： 4 V ~ 6 V
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 28-LCC（J 形引线）
供应商设备封装： 28-PLCC
包装： 管件
TC7135
3.2.1
SYSTEM ZERO
3.2.3
REFERENCE VOLTAGE
Reading = 10 , 000 -----------------------------------------------
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging C AZ (auto-zero capacitor) with a compensat-
ing error voltage. With a zero input voltage, the
integrator output will remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SW I switches. The
internal input points connect to the ANALOG
COMMON pin. The reference capacitor charges to the
reference voltage potential through SW R . A feedback
loop, closed around the integrator and comparator,
INTEGRATION
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero ( see Figure 3-4 ). The digital
reading displayed is:
EQUATION 3-3:
[ Differential Input ]
V REF
charges the C AZ capacitor with a voltage to compen-
sate for buffer amplifier, integrator and comparator
offset voltages (see Figure 3-2 ).
+IN
SW I
Analog
Input Buffer
+ R INT
–
C INT
R INT
–
Integrator –
SW R
–
Integrator –
SW I
+IN
SW R
REF
IN
SW Z
C REF
Analog
Input Buffer
+
–
SW IZ SW Z
SW Z
C INT
C SZ
+
Comparator
+
To
Digital
Section
REF
IN
SW Z
Analog
Common
SW I
IN
C REF
SW 1
SW IZ SW Z
SW Z
C SZ
Comparator
+
+
To
Digital
Section
Switch Open
Switch Closed
Analog
Common
SW I
SW 1
Switch Open
FIGURE 3-4:
Integration Cycle.
Reference Voltage
IN
Switch Closed
FIGURE 3-2:
System Zero Phase.
3.2.4 INTEGRATOR OUTPUT ZERO
This phase ensures the integrator output is at 0V when
3.2.2
ANALOG INPUT SIGNAL
the system zero phase is entered. It also ensures that
INTEGRATION
The TC7135 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range; -1V
from either supply rail, typically. The input signal
the true system offset voltages are compensated for.
This phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5 ).
polarity is determined at the end of this phase.
+IN
SW I
Analog
Input Buffer
+
R INT
C INT
Analog
–
R INT
–
SW I
+IN
SW R
REF
IN
SW Z
C REF
Input Buffer
+
–
SW IZ SW Z
SW Z
C INT
C SZ
–
+
Integrator
Comparator
+
– To
Digital
Section
SW R
REF
IN
SW Z
Analog
Common
SW I
C REF
SW 1
SW IZ SW Z
SW Z
C SZ
Comparator
+
+
– To
Integrator
Digital
Section
Switch Open
Analog
Common
SW I
IN
SW 1
Switch Open
Switch Closed
IN
FIGURE 3-5:
Switch Closed
Integrator Output Zero
Phase.
FIGURE 3-3:
Phase.
Input Signal Integration
? 2007 Microchip Technology Inc.
DS21460D-page 7
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