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参数资料
| 型号： | TC820CPL |
| 厂商： | Microchip Technology |
| 文件页数： | 20/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 3 3/4DGT LGC PROBE 40DIP |
| 标准包装： | 10 |
| 显示器类型： | LCD |
| 配置： | 7 段 + 2 个信号器 |
| 数字或字符： | A/D，3.75 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 9V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 673 (CN2011-ZH PDF) |
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TC820
5.8
Ratiometric Resistance
Measurements
The TC820 true differential input and differential
reference make ratiometric readings possible. In ratio-
+
1μF
+9V
V DD
TC820
metric operation, an unknown resistance is measured
with respect to a known standard resistance. No
accurately defined reference voltage is needed.
DGND
FREQ/VOLTS
The unknown resistance is put in series with a known
standard and a current is passed through the pair
Frequency
Input
74HC14
RANGE/FREQ
is applied to the input and voltages across the known
resistor applied to the reference input. If the unknown
equals the standard, the input voltage will equal the refer-
ence voltage and the display will read 2000. The displayed
reading can be determined from the following expression:
GND
FIGURE 5-9:
Buffer.
DGND
Frequency Counter External
EQUATION 5-3:
5.10
Logic Probe Inputs
Displayed Reading =
R UNKNOWN
R STANDARD
The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either
The display will over range for values of R UNKNOWN
≥ 2 x R STANDARD .
V DD
V REF +
DP0/LO or DP1/HI to a logic high will turn on the
appropriate LCD annunciator. When DP0/LO is high,
the buzzer will be on.
To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in
R STANDARD
V REF -
LCD
ciator on for high and low level inputs.
V IN +
R UNKNOWN
TC820
V IN -
Analog
TC820
+9V
Common
V DD
FIGURE 5-8: Low Parts Count
Ratiometric Resistance Measurement.
5.9 Buffering the FREQ Input
Logic
Probe
Input
*
*
LOGIC
DP1/HI
DP0/LO
When the FREQ/VOLTS input is high and the LOGIC
input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time-base will be F OSC /40,000, or
*74HC14
DGND
1 second with a 40kHz clock. The signal to be
FIGURE 5-10:
Simple External Logic Probe
measured should swing from V DD to DGND. The
RANGE/FREQ input has CMOS input levels without
hysteresis. For best results, especially with low
frequency sine-wave inputs, an external buffer with
hysteresis should be added. A typical circuit is shown
DS21476C-page 20
Buffer.
If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 5-11 shows a
typical circuit. This circuit will turn on the high or low
annunciators when the logic thresholds are exceeded,
but the resistors connected from DP0/LO and DP1/HI
to DGND will turn both annunciators off when the logic
probe is unconnected.
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or
impossible to see. To display short pulses properly, the
input pulse should be "stretched." The circuit of
pull-down resistors to stretch the input pulse and permit
viewing short duration input pulses.
? 2007 Microchip Technology Inc.
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