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参数资料
| 型号： | TC820CPL |
| 厂商： | Microchip Technology |
| 文件页数： | 9/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 3 3/4DGT LGC PROBE 40DIP |
| 标准包装： | 10 |
| 显示器类型： | LCD |
| 配置： | 7 段 + 2 个信号器 |
| 数字或字符： | A/D，3.75 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 9V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 673 (CN2011-ZH PDF) |
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TC820
In a simple dual slope converter, a complete conver-
sion requires the integrator output to "ramp-up" from
zero and "ramp-down" back to zero. A simple mathe-
matical equation relates the input signal, reference
30
T = Measurement
Period
voltage, and integration time.
20
EQUATION 3-1:
∫ 0
V IN (t)dt = REF DEINT
1
R INT C INT
t INT
V t
R INT C INT
10
Where: V REF = Reference Voltage
t INT
= Integration Time
0
t DEINT = De-integration Time
0.1/T
1/T
Input Frequency
10/T
V IN = V REF DEINT
For a constant V INT :
EQUATION 3-2:
t
t INT
FIGURE 3-2: Normal Mode Rejection of
Dual Slope Converter.
3.2 Analog Section
In addition to the basic integrate and de-integrate dual
slope phases discussed above, the TC820 design
incorporates a "zero integrator output" phase and an
Analog
Input Signal
R
C
Integrator
Comparator
"auto-zero" phase. These additional phases ensure
that the integrator starts at 0V (even after a severe over
range conversion), and that all offset voltage errors
(buffer amplifier, integrator and comparator) are
removed from the conversion. A true digital zero
reading is assured without any external adjustments.
REF
Voltage
Switch
Driver
Phase
Control
Polarity Control
Control
Logioc
Clock
A complete conversion consists of four distinct phases:
1. Zero Integrator Output.
2. Auto-Zero.
3.
Signal Integrate.
Display
Counter
4.
Reference De-integrate.
V IN = V REF
V IN = 1.2V REF
3.2.1
ZERO INTEGRATOR OUTPUT
PHASE
Fixed Signal
Integrate Time
FIGURE 3-1:
Variable Reference
Integrate Time
Basic Dual Slope Converter.
This phase guarantees that the integrator output is at
0V before the system zero phase is entered, ensuring
that the true system offset voltages will be compen-
sated for even after an over range conversion. The
Accuracy in a dual slope converter is unrelated to the
integrating resistor and capacitor values as long as
duration of this phase is 500 counts plus the unused
de-integrate counts.
they are stable during a measurement cycle. An
inherent benefit of the dual slope technique is noise
3.2.2
AUTO-ZERO PHASE
immunity. Noise spikes are integrated or averaged to
zero during the integration periods, making integrating
ADCs immune to the large conversion errors that
plague successive approximation converters in high
noise environments. Interfering signals, with frequency
components at multiples of the averaging (integrating)
period, will be attenuated ( Figure 3-2 ). Integrating
ADCs commonly operate with the signal integration
period set to a multiple of the 50/60Hz power line
period.
? 2007 Microchip Technology Inc.
During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by
opening internal analog switches, and the internal
nodes are shorted to Analog Common (0V REF ) to
establish a zero input condition. Additional analog
switches close a feedback loop around the integrator
and comparator to permit comparator offset voltage
error compensation. A voltage established on C AZ then
compensates for internal device offset voltages during
the measurement cycle. The auto-zero phase residual
is typically 10 μV to 15 mV. The auto-zero duration is
1500 counts.
DS21476C-page 9
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