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| 型号： | TC850CPL |
| 元件分类： | ADC |
| 英文描述： | 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 20/26页 |
| 文件大小： | 417K |
| 代理商： | TC850CPL |
2006 Microchip Technology Inc.
DS21479C-page 3
TC850
1.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Positive Supply Voltage..........................................+6V
Negative Supply Voltage ....................................... - 9V
Analog Input Voltage (IN+ pr IN-) .............. VDD to VSS
Voltage Reference Input:
(REF1+, REF1–, REF2+).................. VDD to VSS
Logic Input Voltage............. VDD + 0.3V to GND – 0.3V
Current Into Any Pin...........................................10 mA
While Operating .....................................100
μA
Ambient Operating Temperature Range
C Device....................................... 0°C to +70°C
I Device......................................-25°C to +85°C
Package Power Dissipation (TA ≤ 70°C)
CerDIP .....................................................2.29
Ω
Plastic DIP................................................1.23
Ω
Plastic PLCC ...........................................1.23
Ω
*Stresses
above
those
listed
under
“Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
TABLE 1-1:
TC850 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Zero Scale Error
±0.25
±0.5
LSB
VIN = 0V
End Point Linearity Error
—
±1
±2
LSB
-VFS ≤ VIN ≤ +VFS
Differential Nonlinearity
—
±0.1
±0.5
LSB
IIN
Input Leakage Current
—
30
75
pA
VIN = 0V, TA = 25°C
—
1.1
3
nA
-25°
≤ TA ≤ +85°C
VCMR
Common Mode Voltage Range
VSS + 1.5
—
VSS – 1.5
V
Over Operating Temperature Range
CMRR
Common Mode Rejection Ratio
—
80
—
dB
VIN = 0V, VCM = ±1V
Full Scale Gain Temperature
Coefficient
—
2
5
ppm/°C
External Ref. Temperature
Coefficient = 0 ppm/°C
0°C
≤ TA ≤ +70°C
Zero Scale Error
Temperature Coefficient
—
0.3
2
μV/°C V
IN = 0V
0°C
≤ TA ≤ +70°C
Full Scale Magnitude
Symmetry Error
—
0.5
2
LSB
VIN = ±3.275V
eN
Input Noise
—
30
—
μV
P-P
Not Exceeded 95% of Time
IS+
Positive Supply Current
—
2
3.5
mA
IS–
Negative Supply Current
—
2
3.5
mA
VOH
Output High Voltage
3.5
4.9
—
V
IO = 500 μA
VOL
Output Low Voltage
—
0.15
0.4
V
IO = 1.6 mA
IOP
Output Leakage Current
—
0.1
1
μA
Pins 8 -15, High-impedance State
VIH
Input High Voltage
3.5
2.3
—
V
VIL
Input Low Voltage
—
2.1
1
V
IPU
Input Pull-Up Current
—
4
—
μA
Pins 2, 3, 4, 6, 7; VIN = 0V
IPD
Input Pull-Down Current
—
14
—
μA
Pins 1, 5; VIN = 5V
IOSC
Oscillator Output Current
—
140
—
μA
Pin 18, VOUT = 2.5V
Note
1:
2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram.
3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up
resistors to VDD are recommended.
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