参数资料
型号: TC850CPL
元件分类: ADC
英文描述: 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PDIP40
封装: PLASTIC, DIP-40
文件页数: 3/26页
文件大小: 417K
代理商: TC850CPL
2006 Microchip Technology Inc.
DS21479C-page 11
TC850
5.0
PIN DESCRIPTION (ANALOG)
5.1
Differential Inputs (IN+ and IN–)
The analog signal to be measured is applied at the IN+
and IN– inputs. The differential input voltage must be
within the Common mode range of the converter. The
input Common mode range extends from VDD - 1.5V to
VSS +1.5V. Within this Common mode voltage range,
an 80 dB CMRR is typical.
The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. A worst-case condition exists, for example,
when a large, positive Common mode voltage, with a
near full scale negative differential input voltage, is
applied. The negative input signal drives the integrator
positive when most of its available swing has been
used up by the positive Common mode voltage. For
applications where maximum Common mode range is
critical, integrator swing can be reduced. The integrator
output can swing within 0.4V of either supply without
loss of linearity.
5.2
Differential Reference (VREF)
The TC850 requires two reference voltage sources in
order to generate the “fast-slow” de-integrate phases.
The main voltage reference (VREF1) is applied between
the REF1+ and REF- pins. The secondary reference
(VREF2) is applied between the REF2+ and REF- pins.
The reference voltage inputs are fully differential and
the reference voltage can be generated anywhere
within the power supply voltage of the converter. How-
ever, to minimize rollover error, especially at high con-
version rates, keep the reference Common mode
voltage (i.e., REF-) near or at the analog common
potential. All voltage reference inputs are high-imped-
ance. Average reference input current is typically only
30 pA.
5.3
Analog Common (ANALOG
COMMON)
Analog common is used as the IN- return during the
zero integrator and de-integrate phases of each con-
version. If IN- is at a different potential than analog
common, a Common mode voltage exists in the sys-
tem. This signal is rejected by the 80dB CMRR of the
converter. However, in most applications, IN- will be set
at a fixed, known voltage (power supply common, for
instance). In this case, analog common should be tied
to the same point so that the Common mode voltage is
eliminated.
相关PDF资料
PDF描述
TC850IJL 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, CDIP40
TC850ILW713 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PQCC44
TC850ILWTR 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PQCC44
TC850CLW 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PQCC44
TC850CLWTR 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PQCC44
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