参数资料
型号: TCA8418EYFPR
厂商: TEXAS INSTRUMENTS INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, BGA25
封装: 2 X 2 MM, 0.40 MM PITCH, DSBGA-25
文件页数: 2/31页
文件大小: 400K
代理商: TCA8418EYFPR
V
CC
V
POR
V
PORF
Time
POR
Time
SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
www.ti.com
Figure 4. VPOR
For proper operation of the power-on reset feature, use as directed in the figures and table above.
Interrupt Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge
(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the
ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the input port register.
The INT output has an open-drain structure and requires a pullup resistor to VCC depending on the application. If
the INT signal is connected back to the processor that provides the SCL signal to the TCA64xxA, then the INT
pin has to be connected to VCC. If not, the INT pin can be connected to VCCP.
For more information on the interrupt output feature, see Control Register and Command Byte and Typical
Applications.
50 Micro-second Interrupt Configuration
The TCA8418E provides the capability of deasserting the interrupt for 50 ms while there is a pending event.
When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is
already asserted results in a 50 ms deassertion. When the INT_CFG bit is cleared, processor interrupt remains
asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and
edge triggering applications.
I
2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
10
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TCA8418E
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