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SCPS222B – MAY 2010 – REVISED SEPTEMBER 2010
BIT
NAME
DESCRIPTION
2
KEC2
Key event count, Bit 2
1
KEC1
Key event count, Bit 1
0
KEC0
Key event count, Bit 0
KEC[3:0]: indicates how many registers have values in it. For example, KS(0000) = 0 events, KS(0001) = 1 event
and KS(1010) = 10 events. As interrupts happen (press or release), the count increases accordingly.
Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0×04–0×0D)
BIT
ADDRESS
REGISTER NAME(1)
REGISTER DESCRIPTION
7
6
5
4
3
2
1
0
KEA
KEA6
KEA4
KEA3
KEA1
0×04
KEY_EVENT_A
Key event register A
7
5
2
0
(1)
Only KEY_EVENT_A register is shown
These registers – KEY_EVENT_A-J – function as a FIFO stack which can store up to 10 key presses and
releases. The user first checks the INT_STAT register to see if there are any interrupts. If so, then the Key Lock
and Event Counter Register (KEY_LCK_EC, register 0x03) is read to see how many interrupts are stored. The
INT_STAT register is then read again to ensure no new events have come in. The KEY_EVENT_A register is
then read as many times as there are interrupts. Each time a read happens, the count in the KEY_LCK_EC
register reduces by 1. The data in the FIFO also moves down the stack by 1 too (from KEY_EVENT_J to
KEY_EVENT_A). Once all events have been read, the key event count is at 0 and then KE_INT bit can be
cleared by writing a ‘1’ to it.
In the KEY_EVENT_A register, KEA[6:0] indicates the key # pressed or released. A value of 0 to 80 indicate
which key has been pressed or released in a keypad matrix. Values of 97 to 114 are for GPI events.
Bit 7 or KEA[7] indicate if a key press or key release has happened. A ‘0’ means a key release happened. A ‘1’
means a key has been pressed (which can be cleared on a read).
For example, 3 key presses and 3 key releases are stored as 6 words in the FIFO. As each word is read, the
user knows if it is a key press or key release that occurred. Key presses such as CTRL+ALT+DEL are stored as
3 simultaneous key presses. Key presses and releases generate key event interrupts. The KE_INT bit and /INT
pin will not cleared until the FIFO is cleared of all events.
All registers can be read but for the purpose of the FIFO, the user should only read KEY_EVENT_A register.
Once all the events in the FIFO have been read, reading of KEY_EVENT_A register will yield a zero value.
Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0×0E)
BIT
ADDRESS
REGISTER NAME(1)
REGISTER DESCRIPTION
7
6
5
4
3
2
1
0
0×0E
KP_LCK_TIMER
Keypad lock 1 to lock 2 timer
KL7
KL6
KL5
KL4
KL3
KL2
KL1
KL0
(1)
Only KEY_EVENT_A register is shown
KL[2:0] are for the Lock1 to Lock2 timer
KL[7:3] are for the interrupt mask timer
The interrupt mask timer should be set for the time it takes for the LCD to dim or turn off.
Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address o0×0F)
BIT
ADDRESS
REGISTER NAME(1)
REGISTER DESCRIPTION
7
6
5
4
3
2
1
0
UK1_
UK1
UK1_
UK1
UK1_
UK1
0×0F
Unlock1
Unlock key 1
7
6
_5
4
3
_2
1
_0
(1)
Only KEY_EVENT_A register is shown
Copyright 2010, Texas Instruments Incorporated
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