参数资料
型号: TDA7572
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP64
封装: ROHS COMPLIANT, HIQUAD-64
文件页数: 44/64页
文件大小: 1052K
代理商: TDA7572
TDA7572
Diagnostics
10.1.2
Die temperature
I2Cbus: The Twarn bit in register Faults2 bus register is set when the first threshold is
exceeded. If the second threshold is exceeded the SCR is enabled (only if the
PassFETctrl bit is set to one) which allows the external power switch to latch off, and
can only be restarted by removing and reapplying power. Twarn is cleared using the
W1TC procedure.
No I2Cbus: Operates as above, except the non-latched version (real-time version) of
the Twarn bit is reported on the Address0/Fault_L pin. The value of PassFETctrl is
determined by the SDA/SCR_Enb pin, which is read at powerup.
10.1.3
External temperature
I2C bus: The ExtTwarn bit is set if the voltage at the NTC pin exceeds the first
threshold. If the second threshold is exceeded the SCR is enabled (only if the
PassFETctrl register is set to one). ExtTwarn is cleared by the W1TC procedure
No I2C bus: Operates as above, except the non-latched version (real-time version) of
ExtTwarn register is reported on the Address0/Fault pin. The value of PassFETctrl bit is
determined by the SDA/SCR_Enb pin, which is read at powerup
10.1.4
Output clipping
I2C bus: The Clip bit in the Faults2 register is set when the clipping detected. The Clip
bit is cleared by the W1TC procedure. Clipping is detected if there is maximum
modulation or over current control at the modulator, or if the AOUT pin clips.
No I2C bus: The instantaneous value of clipping, as defined above, is reported on the
SCL/CLIP_L pin. The pin is pulled low during a clipping event (assertion level low).
DAC Enabled: To handle the case when the DAC is in use and to meet the requirement
of a physical clipping signal, the clipping signal is brought out to the Addr0/Fault pin
10.1.5
Output over-current
I2C bus: The output current is clipped/limited by pulse injection into the modulator when
the qualified VDS of the active FET exceeds the first threshold, at the same time the
IoutTrip bit is set. If the second threshold is exceeded the current is cycle-by-cycle
limited by switching the FET's off after few microsecond. If the cycle-to-cycle limitation
is present for more then 4 cycle the SCR is enabled (only if the PassFETctrl register is
set to one) and the external FET are tristated. In case of the SCR is disabled the
external FET are not tristated and the limitation still going. The register is cleared by the
W1TC procedure.
No I2Cbus: In addition to the above, the clipping out pin is engaged by the current
limitation. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which
is read at powerup
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