参数资料
型号: TEA1753LT/N1,518
厂商: NXP Semiconductors
文件页数: 9/32页
文件大小: 0K
描述: IC CTLR SMPS SW MODE 16SO
标准包装: 2,500
系列: GreenChip™ III
输出隔离: 隔离
频率范围: 100kHz ~ 150kHz,250kHz
输入电压: 16 V ~ 38 V
输出电压: 650V
功率(瓦特): 600mW
工作温度: -40°C ~ 150°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SO
包装: 带卷 (TR)
NXP Semiconductors
TEA1753LT
HV start-up flyback controller with integrated PFC controller
7.1.3 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.4 Latch input
The LATCH pin is a general-purpose input pin, which is used to switch off both converters.
The pin sources a current I O(LATCH) of 80 ? A. Switching is stopped as soon as the voltage
on this pin drops below 1.25 V.
At initial start-up, switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V. No internal filtering is done on this pin. An internal Zener clamp of 2.9 V
protects this pin from excessive voltages.
7.1.5 Fast latch reset
In a typical application, the mains is interrupted briefly to reset the latched protection. The
PFC bus capacitor, C bus , does not have to discharge for this latched protection to reset.
When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the
latched protection is reset.
The latched protection is also reset by removing the voltage on the V CC and HV pins.
7.1.6 Overtemperature protection
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shut-down temperature, the IC stops switching. As long
as OTP is active, the capacitor C VCC is not recharged from the HV mains. If the V CC
supply voltage is not sufficient, the OTP circuit is supplied from the HV pin.
OTP is a latched protection. It is reset by removing the voltage on the V CC and HV pins or
by the fast latch reset function. (See Section 7.1.5 )
7.2 Power factor correction circuit
The power factor correction circuit operates in quasi-resonant or Discontinuous
Conduction Mode (CDM) with valley switching. The next primary stroke is only started
when the previous secondary stroke has ended and the voltage across the PFC MOSFET
has reached a minimum value. V PFCAUX is used to detect transformer demagnetization
and the minimum voltage across the external PFC MOSFET switch.
7.2.1 t on control
The power factor correction circuit is operated in t on control. The resulting mains harmonic
reduction is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. To reduce switching losses and electromagnetic
Interference (EMI) (valley switching), the next stroke is started if the voltage across the
PFC MOSFET is at its minimum.
TEA1753LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 August 2012
? NXP B.V. 2012. All rights reserved.
9 of 32
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