参数资料
型号: TEA5760UK/N1/S21,0
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA25
封装: 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25
文件页数: 7/37页
文件大小: 209K
代理商: TEA5760UK/N1/S21,0
TEA5760UK_1
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2006
14 of 36
NXP Semiconductors
TEA5760UK
Single chip FM stereo radio
7.1.1 Interrupt clearing
The interrupt ag and mask bits are always cleared after:
They have been read via the control interface
A power-on reset
7.1.2 Timing
The timing sequence for the general operation interrupts is shown in Figure 5 shows a
read access of the interrupt register INTREG and a subsequent (though not necessarily
immediate) write to the mask register. It also indicates two key timing points A and B.
If an interrupt event occurs while the register is being read (after point A) it must be held
until after the mask register is cleared at the end of the read operation (point B).
Point A is dened as: the R/W bit has been decoded. Point B is where the acknowledge
has been received from the master after the rst two bytes have been sent.
The low time for the INTX line (tp) has a maximum value specied in Section 11. It can be
shorter when a read action of the INTREG registers occurs within tp.
7.1.3 Reset
A reset can be performed (at any time) by a simple read of the interrupt register (byte0R
and byte1R), which automatically clears the interrupt ags and masks.
7.1.4 Interrupt ags and behavior
7.1.4.1
Multiple interrupt events
If the interrupt mask register bit is set then the setting of an interrupt ag for that bit
causes a HW interrupt (INTX goes LOW). If the event occurs again, before the ag is
cleared, then this does not trigger any further HW interrupts until that specic ag is
cleared. However two different events can occur in sequence and generate a sequence of
HW interrupts.
Only when read, followed by a write of the INTMSK byte has been done, can a second
interrupt can be generated, as the rst interrupt blocks the input of the INTX oneshot
generator.
If subsequent interrupts occur within the INTX LOW period then these do not cause the
INTX period to extend beyond its specied maximum period (see Section 7.2).
7.1.4.2
IF frequency: IFFLAG
During automatic frequency search or preset, the FM part of the TEA5760UK performs a
check on the received IF frequency. If an incorrect IF frequency is received then this
indicates the presence of strong interference or tuning to the image frequency. In case of
preset tuning or search tuning with the AHLSI bit set the IFFLAG will be set and the
algorithm will stop. When a search or preset is nished the FRRFLAG will be set and an
interrupt is generated if the corresponding mask bit is set. The host processor can now
read the outcome of the registers which will contain the IF count value and the IFFLAG
status of the channel it is tuned to.
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