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参数资料
| 型号： | TEA5766UK/N1/S21,1 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 接收器 |
| 英文描述： | FM, AUDIO SINGLE CHIP RECEIVER, PBGA25 |
| 封装： | 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件页数： | 27/59页 |
| 文件大小： | 273K |
| 代理商： | TEA5766UK/N1/S21,1 |
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TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
33 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
[1]
The maximum fall time for the SDA and SCL bus lines quoted in table 5 of Ref. 1, 300 ns, is shorter than the specied maximum for the
output stages, 350 ns, therefore no series protection resistors may be connected between the SDA and SCL pins and the SDA and SCL
bus lines as shown in gure 36 of Ref. 1.
10.2.3 I2C-bus timing diagram
Table 10.
Characteristics of the data output stage for fast mode and standard mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL1
LOW-level output
voltage
open collector; Isink = 2 mA; VVREFDIG >2V
standard mode
0
-
0.5
V
fast mode
0
-
0.5
V
VOL3
LOW-level output
voltage
fast mode; open collector; Isink = 2 mA;
VVREFDIG <2V
0
-
0.5
V
tof
output fall time
standard mode
250
-
350
ns
fast mode
250
-
350
ns
In TEA5766UK, signal SDA is present on pin DATA and signal SCL on pin CLOCK.
Cb = capacitive load for each bus line: < 100 pF.
tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 350 ns, where Cb = total capacitance on bus line in pF.
tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 350 ns, where Cb = total capacitance on bus line in pF.
tHD;STA = hold time (repeated) START condition. After this period, the rst clock pulse is generated: > 600 ns.
tHIGH = HIGH period of the SCL clock: > 600 ns.
tLOW = LOW period of the SCL clock: > 1.3 s
tSU;STA = set-up time for a repeated START condition: > 600 ns.
tHD;DAT = data hold time: 300 ns < tHD;DAT < 900 ns.
Remark: 300 ns lower limit is added because the TEA5766UK has no internal hold time for the SDA signal.
tSU;DAT = data set-up time: > 100 ns. If TEA5766UK is used in a standard mode I2C-bus system, tSU;DAT > 250 ns.
tSU;STO = set-up time for STOP condition: > 600 ns.
tBUF = bus free time between a STOP and a START condition: > 600 ns.
tsu(BUSEN) = set-up time on pin BUSEN (bus enable): > 10 s.
th(BUSEN) = hold time on pin BUSEN: > 10 s.
Fig 16. I2C-bus timing diagram
P
S
Sr
P
001aaf518
tHD;STA
tBUF
tSU;STA
tSU;DAT
tf
tHIGH
tLOW
tSU;STO
tr
tHD;DAT
SDA
SCL
BUSEN
tsu(BUSEN)
th(BUSEN)
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