TFP7401
SXGA+/UXGA TFT LCD PANEL TIMING CONTROLLER
WITH MINILVDS AND FLATLINK
SLDS126 – APRIL 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Mini-LVDS Intra-Panel Interface for Low
Power and Low EMI
D Drives TI Mini-LVDS Source Drivers at 292
Mbps With a 146 MHz Clock
D 6-Bits LVDS Video System Interface
(FlatLinK
)
D Support Both 2 Level and 3 Level Gate
Drivers
D Ability to Drive SXGA+/UXGA TFT-LCD
System
D Optional EEPROM Allows Fine Tuning in
Development and Production
Environments
D Narrow 4 Pair Differential Source Driver
Bus Minimizes Width of PCB
D Failure Detection of Input Clock With
Default Source Driver Control Generation
D CMOS 3.3 V Technology
description
This panel timing controller consists of FlatLink, mini-LVDS and a TFT-LCD timing controller. It resides on the
TFT-LCD module and provides interface timing control between graphics or video controllers and a TFT LCD
system. FlatLink, a low power, low EMI (electromagnetic Interference) LVDS interface, is used between this
controller and the host system. A mini-LVDS intra-panel interface is used between the timing controller and
source drivers.
Programmable outputs provide a mini-LVDS source driver and 2/3 level gate driver control. This timing controller
is configured via metal mask initialization value or an optional external serial EEPROM.
PRODUCT
PREVIEW
Copyright
2001, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.