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参数资料
| 型号： | TFP7401 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 4/7页 |
| 文件大小： | 130K |
| 代理商： | TFP7401 |
TFP7401
SXGA+/UXGA TFT LCD PANEL TIMING CONTROLLER
WITH MINILVDS AND FLATLINK
SLDS126 – APRIL 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
block diagram
SDA
SCL
Control
Logic
FlatLink
Fail-Safe
Circuit
Data
Alignment
EEPROM
Serial
Interface
STVA, STVB
CPV
(Data Pair)
SXGA+ : 4 Pair x 2
UXGA : 5 Pair x 2
Mini-LVDS
Transmitter
Timing
Generator
Source Driver
Control Timings
Gate Driver
Control Timings
Power
Down
Detector
TP1, POL
E2UPDATE, R1,
RCLKIN,
RCLKOUT1,
RCLKOUT2
DC/DC
Converter
Control
T1, T2
XRESET, CEXT,
ENVDET, PGM1,
XAGING, TEST,
ORXIN
ORXCLK
ERXIN
ERXCLK
3 Pair
1 Pair
3 Pair
1 Pair
(Clock Pair)
2 Pair
OE
detailed description
FlatLink receiver
The core of the FlatLink is TI’s original 82A LVDS receiver, which has three data channels for 18-bit color and
one clock channel. The receiver block supports up to dual LVDS bus.
data alignment and mini-LVDS transmitter
The data alignment block supports dual mini-LVDS bus configuration. The controller arranges pixel data and
distributes them to left half and right half drivers.
The mini-LVDS source drivers latch data on both positive and negative edges of the clock.
timing control
These blocks generate control to source drivers, gate drivers, and power supply. Both two and three level gate
drivers are supported.
PRODUCT
PREVIEW
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