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参数资料
| 型号： | THS1007IDA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 8/34页 |
| 文件大小： | 364K |
| 代理商： | THS1007IDA |
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THS1007
SLAS286B AUGUST 2000 REVISED DECEMBER 2010
www.ti.com
16
Conversion
During conversion, the ADC operates with a free running external clock applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the data bus with the
corresponding read signal. The THS1007 allows up to four analog inputs to be selected. The inputs can be
configured as two differential channels, four single-ended channels or a combination of differential and
signle-ended.
To provide the system with channel information, the THS1007 utilizes an active low SYNC signal. When
operated in a multichannel configuration, the SYNC signal is active low when data from channel 1 is available
to the databus. When operated in signle-channel mode (single-ended or differential operation) the SYNC signal
is disabled.
Figure 28 shows the timing of the conversion, when one analog input channel is selected. The maximum
throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since
this information is not necessary. There is a certain timing relationship required for the read signal with respect
to the conversion clock. This can be seen in Figure 28 and the timing specifications. A more detailed description
of the timing is given in the timing section and signal description of the THS1007.
Sample N
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+1
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Data N1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N4
Channel 1
Data N3
Channel 1
Data N2
Channel 1
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
Figure 28. Conversion Timing in 1-Channel Operation
Figure 29 shows the conversion timing when two analog input channels are selected. The maximum throughput
rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted
data is available to the data bus. The SYNC pulse is active low when the data of channel one is available to
the databus. The data of channel one is followed by the data of channel two before the SYNC signal is active
low again.
相关PDF资料 |
PDF描述 |
|---|---|
| THS1007IDAR | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS1007IDAG4 | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS10082CDAG4 | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS10082CDAR | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS10082CDA | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| THS1007IDAG4 | 功能描述:模数转换器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS1007IDAR | 制造商:TI 制造商全称:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS10082 | 制造商:TI 制造商全称:Texas Instruments 功能描述:10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER |
| THS10082CDA | 功能描述:模数转换器 - ADC 10 Bit 8 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS10082CDAG4 | 功能描述:模数转换器 - ADC 10 Bit 8 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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