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参数资料
| 型号： | THS1030CPWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 33/37页 |
| 文件大小： | 727K |
| 代理商： | THS1030CPWR |
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THS1030
3V TO 5.5V, 10BIT, 30 MSPS
CMOS ANALOGTODIGITAL CONVERTER
SLAS243E NOVEMBER 1999 REVISED DECEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 30
MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference,
TA = Tmin to Tmax (unless otherwise noted) (continued)
dc accuracy
PARAMETER
MIN
TYP
MAX
UNIT
INL
Integral nonlinearity (see Note 2)
±1
±2
LSB
DNL
Differential nonlinearity (see Note 3)
±0.3
±1
LSB
Offset error (see Note 4)
0.4
1.4
%FSR
Gain error (see Note 5)
1.4
3.5
%FSR
Missing code
No missing code assured
NOTES:
2. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.
3. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level)
÷ (2 n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.
4. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
5. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (1024).
dynamic performance (See Note 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 3.5 MHz
8.4
9
ENOB
Effective number of bits
f = 3.5 MHz, AVDD = 5 V
9
Bits
ENOB
Effective number of bits
f = 15 MHz, 3 V
7.8
Bits
f = 15 MHz, AVDD = 5 V
7.7
f = 3.5 MHz
56
60.6
SFDR
Spurious free dynamic range
f = 3.5 MHz, AVDD = 5 V
64.6
dB
SFDR
Spurious free dynamic range
f = 15 MHz
48.5
dB
f = 15 MHz, AVDD = 5 V
53
f = 3.5 MHz
60
56
dB
THD
Total harmonic distortion
f = 3.5 MHz, AVDD = 5 V
66.9
dB
THD
Total harmonic distortion
f = 15 MHz
47.5
f = 15 MHz, AVDD = 5 V
53.1
f = 3.5 MHz
53
57
dB
SNR
Signal-to-noise ratio
f = 3.5 MHz, AVDD = 5 V
56
dB
SNR
Signal-to-noise ratio
f = 15 MHz
53.1
f = 15 MHz, AVDD = 5 V
49.4
f = 3.5 MHz
52.5
56
SINAD
Signal-to-noise and distortion
f = 3.5 MHz, AVDD = 5 V
56
dB
SINAD
Signal-to-noise and distortion
f = 15 MHz
48.6
dB
f = 15 MHz, AVDD = 5 V
48.1
NOTES:
6. Input amplitude of single tone sine wave for dynamic tests is 0.5 dBFS.
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