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参数资料
| 型号： | THS1206IDARG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 21/43页 |
| 文件大小： | 722K |
| 代理商： | THS1206IDARG4 |
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THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
28
FIFO TRIGGER LEVEL
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger
level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to
indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be
selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered as one
channel. The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between
the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
TRIGGER LEVEL
FOR 3 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 4 CHANNELS
(ADC values)
0
01
02
03
04
0
1
04
06
08
1
0
08
09
12
1
14
12
Reserved
TIMING AND SIGNAL DESCRIPTION OF THE THS1206
The reading from the THS1206 and writing to the THS1206 is performed by using the chip select inputs (CS0, CS1), the
write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired
in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs
can be used to interface easily to a processor.
Reading from the THS1206 takes place by an internal RDint signal, which is generated from the logical combination of the
external signals CS0, CS1 and RD (see Figure 35). This signal is then used to strobe the words out of the FIFO and to
enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RDint active while
the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates RDint again.
Writing to the THS1206 takes place by an internal WRint signal, which is generated from the logical combination of the
external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid makes WRint active while the read input (RD) is inactive.
The first of those external signals going to its inactive state then deactivates WRint again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 35. Logical Combination of CS0, CS1, RD, and WR
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相关代理商/技术参数 |
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| THS1206MDA | 制造商:Texas Instruments 功能描述:ADC SGL PIPELINED 6MSPS 12-BIT PARALLEL 32TSSOP - Tape and Reel |
| THS1206MDAREP | 功能描述:模数转换器 - ADC EP 12B,6Msps ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS1206M-EVM | 功能描述:数据转换 IC 开发工具 THS1206M Eval Module RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| THS1206QDA | 功能描述:模数转换器 - ADC 12-Bit 6 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS1206QDAR | 功能描述:模数转换器 - ADC 12 Bit 6 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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