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参数资料
| 型号： | THS1207CDA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 8/32页 |
| 文件大小： | 317K |
| 代理商： | THS1207CDA |
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THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
16
Figure 28 shows the conversion timing when 3 analog input channels are selected. The maximum throughput
rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel one is
available to the databus. The data of channel one is followed by the data of channel two and data of channel
three before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3
Sample N+1
Channel 1, 2, 3
Sample N+2
Channel 1, 2, 3
Data N–1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N–2
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Figure 28. Conversion Timing in 3-Channel Operation
Figure 29 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum
throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the databus. The signal SYNC is active low when data of channel one
is available to the databus. The data of channel one is followed by the data of channel two, data of channel three
and data of channel 4 before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3, 4
Sample N+1
Channel 1, 2, 3, 4
Data N–1
Channel 4
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
Data N–1
Channel 3
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCH)
tsu(CONV_CLKL-SYNCL)
Figure 29. Timing of Continuous Conversion Mode (4-channel operation)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| THS1207CDAG4 | 功能描述:模数转换器 - ADC 12-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS1207CDAR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| THS1207EVM | 制造商:Texas Instruments 功能描述:THS1207 ANALOG TO DIGITAL CONVERTER EVM - Bulk |
| THS1207IDA | 功能描述:模数转换器 - ADC 12-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| THS1207IDAG4 | 功能描述:模数转换器 - ADC 12-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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