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参数资料
| 型号： | THS1230IDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, SOIC-28 |
| 文件页数： | 9/25页 |
| 文件大小： | 854K |
| 代理商： | THS1230IDWRG4 |
www.ti.com
AGND
1
CON1
2
CON0
3
EXTREF
4
AIN+
5
AIN
6
AGND
7
AVDD
8
REFT
9
REFB
10
OVRNG
11
D11
12
D10
13
D9
14
D8
15
D7
16
D6
17
D5
18
DGND
19
DVDD
20
D4
21
D3
22
D2
23
D1
24
D0
25
OE
26
CLKVDD
27
CLK
28
U1
THS1230PW
+3.3VA
+3.3VD +3.3VA
ADCCLK
OEB
CON0
CON1
EXTREF
VINP
VINM
ADCCLK
OEB
CON0
CON1
EXTREF
VINM
D4
10
D5
9
D6
8
D7
7
D8
6
D9
5
D10
4
D11
3
D12
2
D13
1
CLK
28
MODE
25
DVDD
27
DGND
26
AGND
20
AVDD
24
EXTLO
16
REFIO
17
FSADJ
18
COMP1
19
COMP2
23
IOUT1
22
IOUT2
21
SLEEP
15
D3
11
D2
12
D1
13
D0
14
U3
THS5671AIPW
LNK3
LNK2
LNK4
LNK5
R2
47K
R23
47K
R1
47K
R24
47K
+3.3VD
OEB
EXTREF
CON1
CON0
TP1
TP2
+
C28
10uF
C27
0.1uF
C25
0.1uF
C26
0.1uF
VRT
VRB
VRT
VRB
C62
470pF
C63
0.1uF
C64
470pF
C65
0.1uF
C66
470pF
C67
0.1uF
+3.3VD
_3.3VA
ADCOVRNG
ADCD00
ADCD01
ADCD02
ADCD03
ADCD04
ADCD05
ADCD06
ADCD07
ADCD08
ADCD09
ADCD10
ADCD11
ADCD [00:11]
+3.3VA
+3.3VD
ADCDB00
ADCDB01
ADCDB02
ADCDB03
ADCDB04
ADCDB05
ADCDB06
ADCDB07
ADCDB08
ADCDB09
ADCDB10
ADCDB11
ADCDB[00:11]
DACCLK
C6
0.1uF
C15
0.1uF
+3.3VA
IOUT1
IOUT2
R10
2K
C16
0.01uF
C5
0.1uF
C19
10uF
C17
0.1uF
C18
0.1uF
+3.3VD
+3.3VA
CON1
OEB
EXTREF
IOUT1
IOUT2
+
VINP
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset and Gain Error
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 22. EVM Schematic
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2
LSB beyond the last code transition. The deviation is measured from the center of each particular code to the
true straight line between these two end-points.
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined
here as the step size for the device under test, i.e. (last transition level - first transition level)/(2n –2). Using this
definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no
missing codes.
Offset error (in LSBs) is defined as the average offset for all inputs, and gain error is defined as the maximum
error (in LSBs) caused by the angular deviation from the offset corrected straight line.
17
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| THS1230IPWG4 | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
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