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参数资料
| 型号： | TLC1551INW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24 |
| 封装： | PLASTIC, DIP-24 |
| 文件页数： | 10/10页 |
| 文件大小： | 141K |
| 代理商： | TLC1551INW |
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043F – MAY 1991 – REVISED JANUARY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550
and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder
output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.
Once CS is low, the onboard system clock permits the conversion to begin with a simple write command and the
converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)
mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.
After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the
end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.
Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.
0.8 V
1.4 V
2 V
1.4 V
0.8 V
2 V
0.8 V
2 V
0.8 V
2 V
0.8 V
tsu(CS)
th(CS)
tw(WR)
tc
tsu(CS)
th(CS)
tdis(D)
tv(D)
ta(D)
td(EOC)
0.8 V
2 V
CS
WR
RD
EOC
D0 – D9
Data Valid
Figure 3. TLC1550 or TLC1551 Operating Sequence
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