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参数资料
| 型号： | TLC2543QDWRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 7/25页 |
| 文件大小： | 413K |
| 代理商： | TLC2543QDWRQ1 |
TLC2543Q1
12BIT ANALOGTODIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS218D NOVEMBER 2003 REVISED MAY 2008
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
data output length
The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is
valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the
current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can
be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
In actual operation, when different data lengths are required within an application and the data length is changed
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB-first format.
sampling period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the 8th, 12th, or 16th falling edge of the I/O
CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK falling edge,
the EOC output goes low indicating that the sampling period is over and the conversion period has begun. After
EOC goes low, the analog input can be changed without affecting the conversion result. Since the delay from
the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be digitized
at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
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