参数资料
型号: TLC2933AIPWRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 1 MHz, PDSO14
封装: ROHS COMPLIANT, PLASTIC, TSOP-14
文件页数: 17/23页
文件大小: 522K
代理商: TLC2933AIPWRG4
TLC2933A
HIGH PERFORMANCE PHASE LOCKED LOOP
SLES149 OCTOBER 2005
3
TI.COM
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external register (RBIAS) connected between the VCO VDD
and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock
frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
Bias Resistor (RBIAS)
VCO Oscillation Frequency Range
1/2 VDD
VCO Control Voltage (VCO IN)
VCO
Oscillation
Frequency
f
OSC
Figure 1.
Oscillation Frequency
VCO output frequency 1/2 divider
The TLC2933A SELECT terminal sets the fOSC VCO output frequency as shown in Table 1. The 1/2 fOSC output
should be used for minimum VCO output jitter.
Table 1.
VCO Output 1/2 Divider Function
SELLECT
VCO OUTPUT
Low
fOSC
High
1/2 fOSC
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the powerdown mode as shown in Table 2.
Table 2.
VCO Inhibit Function
VCO INHIBIT
VCO OSCILLATOR
VCO OUT
IDD(VCO)
Low
Active
Normal
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FINA and FINB as shown in Figure 2. Normally the
reference is supplied to FINA and the frequency from the external counter output is fed to FINB. For clock
recovery PLL system, other types of phase detectors should be used.
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