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参数资料
| 型号： | TLC5945RHBT |
| 厂商： | Texas Instruments |
| 文件页数： | 11/30页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 32-QFN |
| 标准包装： | 250 |
| 恒定电流： | 是 |
| 拓扑： | PWM |
| 输出数： | 16 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 颜色 |
| 频率： | 30MHz |
| 电源电压： | 3 V ~ 5.5 V |
| 输出电压： | 17V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
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TLC5945
www.ti.com
SLVS755 – MARCH 2007
PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5945 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK
signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of
XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of
XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending
on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle.
Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the
grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the
existing grayscale data. Figure 6 shows the timing chart. More than two TLC5945s can be connected in series
by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5945s is shown in Figure 7 . The SOUT pin can also be connected to the controller to receive status
information from TLC5945 as shown in Figure 16 .
MODE
DC Data Input Mode
GS Data Input Mode
XLAT
th3
tsu3
1st GS Data Input Cycle
2nd GS Data Input Cycle
twh2
SIN
DC
MSB
DC
LSB
th2
GS1
MSB
tsu2
GS1
LSB
tsu1
th1
GS2
MSB
twh0
GS2
LSB
tsu0
GS3
MSB
th0
SCLK
1
96
1
192
193
1
192
193
1
twl0
tpd0
SOUT
-
DC
MSB
-
-
GS1
MSB
SID1 SID1
MSB MSB-1
SID1
LSB
GS2
MSB
SID2 SID2
MSB MSB-1
twh3
BLANK
1st GS Data Output Cycle
2nd GS Data Output Cycle
tsu5
th4
tsu4
twh1
GSCLK
1
4096
1
OUT0
tpd4
tpd1
tpd3
tpd3
Tgsclk
twl1
(current)
OUT1
(current)
OUT15
(current)
XERR
tpd2
Figure 6. Serial Data Input Timing Chart
tpd3
touton
SIN(a)
SIN
SOUT
SIN
SOUT
SOUT(b )
TLC5945 (a)
TLC5945 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 7. Cascading Two TLC5945 Devices
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