参数资料
型号: TLE6286G
厂商: INFINEON TECHNOLOGIES AG
元件分类: Buffer和线驱动
英文描述: LINE TRANSCEIVER, PDSO16
封装: PLASTIC, SOP-16
文件页数: 2/23页
文件大小: 424K
代理商: TLE6286G
Preliminary Data Sheet
10
Rev. 1.20, 2005-04-13
TLE 6286
Figure 4
Typical Reset Delay Timing vs. Delay Capacitance
The reset reaction time
t
rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1
s
for delay capacitor of 47 nF. For other values for
C
D the reaction time can be estimated
using the following equation:
t
rr ≈ 20 s/F × CD
(2)
For the reset timing diagram please refer to Figure 6.
Watchdog Timing
The frequency of the watchdog pulses has to be higher than the minimum pulse
sequence which is set by the external reset delay capacitor
C
D. Calculation can be done
according to the formulas given in Figure 5. For the watchdog timing diagram please
refer to Figure 7.
T
WI,tr = [(VDU × VDWL) / ID,wd] / CD
(3)
Definitions:
T
WI,tr = watchdog trigger time
I
D,wd = discharge current, typical 6.25 A
V
DWL = lower timing threshold
A E D 0 34 67 . V S D
t
rd
nF
C
D
0
50
100
150
200
250
300
350
400
0
1
2
3
4
5
6
7
8 ms 1 0
C
D =
( t
rd x I D, c h )
V
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