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| 型号： | TLK4201EA |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 4.25 Gbps Cable And PC Board Equalizer |
| 中文描述： | 4.25Gbps 电缆和 PC 主板均衡器 |
| 文件页数： | 10/17页 |
| 文件大小： | 727K |
| 代理商： | TLK4201EA |
www.ti.com
BLOCK DIAGRAM
DOUT+
DOUT
DIN+
DIN
+
Gain Stage
+
COC2
COC1
DISABLE
LOS
VCC
GND
OUTPOL
Bandgap Voltage
Reference and
Bias Current
Generation
Gain Stage
Loss of
Signal Detection
Offset
Cancellation
LOSDIS
CML
Output
Buffer
Stage
B0052-03
Fixed Equalizer
Stage
HIGH-SPEED DATA PATH
LOSS OF SIGNAL DETECTION
BAND-GAP VOLTAGE AND BIAS GENERATION
TLK4201EA
SLLS719 – APRIL 2006
A simplified block diagram of the TLK4201EA is shown in Figure 1. This compact, low-power, 4.25-Gbps
equalizer consists of a high-speed data path with an offset cancellation circuitry, a loss-of-signal detection block,
and a band-gap voltage reference and bias current generation block.
The equalizer requires a single 3.3-V supply voltage. All circuit parts are described in detail as follows.
Figure 1. Simplified Block Diagram of the TLK4201EA
The high-speed data signal with frequency dependent loss is applied to the data path by means of the input
signal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage with 100-
on-chip differential
line termination, three gain stages, which provide the required gain to ensure a limited output signal, and a CML
output stage. The equalized and amplified data output signal is available at the output pins DOUT+/DOUT–,
which provide 2 × 50-
back-termination to VCC. The output stage also includes a data polarity switching
function, which is controlled by the OUTPOL input, and a disable function, controlled by the signal applied to the
DISABLE input pin. An offset cancellation circuit compensates for inevitable internal offset voltages and thus
ensures proper operation even for very small input data signals.
The low-frequency cutoff is as low as 10 kHz with the built-in filter capacitor. For applications which require even
lower cutoff frequencies, an additional external filter capacitor can be connected to the COC1/COC2 pins.
The output signal of the second gain stage is monitored by the loss-of-signal detection circuitry. In this block, the
input signal is compared to a fixed threshold. If the low-frequency components of the input signal fall below this
threshold, a loss of signal is indicated at the LOS pin.
A squelch function can be easily implemented by connecting the LOS output to the adjacent DISABLE input.
This measure avoids chattering of the output when no input signal is present. The LOS function can be disabled
by pulling LOSDIS to high level.
The TLK4201EA equalizer is supplied by a single 3.3V ±10% supply voltage connected to the VCC pins. This
voltage is referred to ground (GND).
An on-chip band-gap voltage circuit generates a supply-voltage-independent reference from which all internally
required voltages and bias currents are derived.
2
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