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参数资料
型号： TLK4201EA
厂商： Texas Instruments, Inc.
英文描述： 4.25 Gbps Cable And PC Board Equalizer
中文描述： 4.25Gbps 电缆和 PC 主板均衡器
文件页数： 13/17页
文件大小： 727K
代理商： TLK4201EA
www.ti.com
AC ELECTRICAL CHARACTERISTICS
TLK4201EA
SLLS719 – APRIL 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
COC = open
10
50
Low frequency –3dB bandwidth
kHz
COC = 0.1 F
0.8
Maximum data rate
4.25
Gbps
VIN,MIN
Data input voltage sensitivity(2)
BER < 10-12, input signal applied
100
120
mVP-P
over 36 inches of 7-mil-wide stripline
interconnect on standard FR4,
voltage at the input of the
interconnect line, K28.5 pattern at
4.25 Gbps.
VIN,MAX
Data input voltage overload
Voltage at the interconnect input
2000
mVP-P
High-frequency boost
f = 2.1 GHz
9
12
16
dB
DISABLE = high
0.25
10
Data differential output voltage
VOD
mVP-P
swing
DISABLE = low
600
780
1200
No board or cable
20
24 inches of
25
7-mil-wide
f = 4.25 GHz,
stripline on
K28.5 pattern,
standard FR4
VIN = 200 mVP-P
DJ
Deterministic jitter
(differential
36 inches of
20
psP-P
voltage at the
7-mil-wide
interconnect
stripline on
input)
standard FR4
30 feet CX4 cable
20
50 feet CX4 cable
35
RJ
Random jitter
VIN = 200 mVP-P (differential voltage
4
psRMS
at the interconnect input)
Latency
From DIN+/DIN– to DOUT+/DOUT–
250
ps
tr
Output rise time
20% to 80%, 4.25 Gbps, no board or
55
85
ps
cable
tf
Output fall time
20% to 80%, 4.25 Gbps, no board or
55
85
ps
cable
tDIS
Disable response time
20
ns
Input signal applied over 36 inches of
7-mil-wide stripline interconnect on
VAS
LOS assert threshold voltage
standard FR4, voltage at the input of
40
80
mVP-P
the interconnect line, K28.5 pattern at
4.25 Gbps.(3)
Input signal applied over 36 inches of
7-mil-wide stripline interconnect on
VDAS
LOS de-assert threshold voltage
standard FR4, voltage at the input of
130
200
mVP-P
the interconnect line, K28.5 pattern at
4.25 Gbps. (3)
K28.5 at 4.25 Gbps over 36 inches of
LOS hysteresis
3
4.5
dB
7-mil-wide stripline on standard FR4
K28.5 at 4.25 Gbps over 36 inches of
tAS/DAS
LOS assert/de-assert time
2
100
s
7-mil-wide stripline on standard FR4
(1)
Typical values are measured at VCC = 3.3 V and TA = 25°C.
(2)
The given differential input signal swing is measured at the input of the interconnect. The high-frequency components of the signal at the
output of the interconnect (connected to input pins DIN+/DIN– of the TLK4201EA) may be attenuated by as much as 12 dB at 2.1 GHz
depending on the interconnect length and attenuation characteristics of the interconnect.
(3)
Depending on the interconnect line length and performance, the bit pattern, and the data rate, the assert and de-assert threshold
voltage levels vary. For more information, see the Typical Characteristics section.
5
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