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参数资料
型号： TLV2544QD
厂商： TEXAS INSTRUMENTS INC
元件分类： ADC
英文描述： 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封装： PLASTIC, SOIC-16
文件页数： 41/43页
文件大小： 989K
代理商： TLV2544QD
TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control and timing (continued)
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions
BIT
DEFINITION
D11
Reference select
0: External
1: internal
D10
Internal reference voltage select
0: Internal ref = 4 V 1: internal ref = 2 V
D9
Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D(87)
Conversion clock source select
00: Conversion clock = internal OSC
01: Conversion clock = SCLK
10: Conversion clock = SCLK/4
11: Conversion clock = SCLK/2
D(6,5)
Conversion mode select
00: Single shot mode [FIFO not used, D(1,0) has no effect.]
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
D(4,3)
TLV2548
TLV2544
D(4,3)
Sweep auto sequence select
00: 01234567
01: 02460246
10: 00224466
11: 02020202
Sweep auto sequence select
00: N/A
01: 01230123
10: 00112233
11: 01010101
D2
EOC/INT pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0)
FIFO trigger level (sweep sequence length)
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).
normal sampling
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short
sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input
source resistance is high.
相关PDF资料
PDF描述
TLV2548QDWG4 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
5962-9957001QRA 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
TLV2548MJ 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
5962-9957601Q2A SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CQCC20
5962-9957601QPA SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, CDIP8
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