参数资料
型号: TLV2544QDRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封装: PLASTIC, SOIC-16
文件页数: 39/43页
文件大小: 989K
代理商: TLV2544QDRG4
TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
serial interface
INPUT DATA FORMAT
MSB
LSB
D15D12
D11D0
Command
Configuration data field
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR
MSB
LSB
D15D12
D11D0
Don’t care
Register content
OUTPUT DATA FORMAT CONVERSION/READ FIFO
MSB
LSB
D15D4
D3D0
Conversion result
Don’t care
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = VREFM
Full scale code = FFFh, Vcode = VREFP 1 LSB
control and timing
power up and initialization requirements
D Determine processor type by writing A000h to the TLV2544/48 (CS must be toggled)
D Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e.,
active FS.)
The first conversion after power up or resuming from power down is not valid.
start of the cycle:
D When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.
D When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.
first 4-MSBs: the command register (CMR)
The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of
the commands require only the first 4 MSBs, i.e., without the 12-bit data field.
NOTE:
The device requires a write CFR (configuration register) with 000h data (write A000h to the serial
input) at power up to initialize host select mode.
The valid commands are listed in Table 1.
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