参数资料
型号: TLV2544QDRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封装: PLASTIC, SOIC-16
文件页数: 40/43页
文件大小: 989K
代理商: TLV2544QDRG4
TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 1. TLV2544/TLV2548 Command Set
SDI D(1512) BINARY
TLV2548 COMMAND
TLV2544 COMMAND
0000b
0h
Select analog input channel 0
0001b
1h
Select analog input channel 1
N/A
0010b
2h
Select analog input channel 2
Select analog input channel 1
0011b
3h
Select analog input channel 3
N/A
0100b
4h
Select analog input channel 4
Select analog input channel 2
0101b
5h
Select analog input channel 5
N/A
0110b
6h
Select analog input channel 6
Select analog input channel 3
0111b
7h
Select analog input channel 7
N/A
1000b
8h
SW power down (analog + reference)
1001b
9h
Read CFR register data shown as SDO D(110)
1010b
Ah plus data
Write CFR followed by 12-bit data, e.g., 0A100h means external reference,
short sampling, SCLK/4, single shot, INT
1011b
Bh
Select test, voltage = (REFP+REFM)/2
1100b
Ch
Select test, voltage = REFM
1101b
Dh
Select test, voltage = REFP
1110b
Eh
FIFO read, FIFO contents shown as SDO D(154), D(30) = 0000
1111b
Fh plus data
Reserved
1111b
Fh plus data
Reserved
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status of
the CFR can be read with a read CFR command when the device is programmed for one-shot conversion mode
(CFR D[6,5] = 00).
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