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| 型号： | TLV2553IDWRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, SOIC-20 |
| 文件页数： | 14/28页 |
| 文件大小： | 414K |
| 代理商： | TLV2553IDWRQ1 |
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Power Up and Initialization
Data Input
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
The entire I/O CLOCK sequence that transfers address and control data into the data register and
Current (N) I/O cycle
clocks the digital result from the previous conversion from DATA OUT
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle
Current (N) conversion cycle
is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded
into the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N – 1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N + 1) I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
CFGR1
COMMAND
CONFIGURATION
BINARY
HEX
SDI D[3:0]
0000
0
SELECT analog input channel 0
01: 8-bit output length
0001
1
SELECT analog input channel 1
D[3:2]
X0: 12-bit output length(1)
0010
2
SELECT analog input channel 2
11: 16-bit output length
0011
3
SELECT analog input channel 3
0: MSB out first
D1
0100
4
SELECT analog input channel 4
1: LSB out first
0101
5
SELECT analog input channel 5
0: Unipolar binary
D0
0110
6
SELECT analog input channel 6
1: Bipolar 2s complement
0111
7
SELECT analog input channel 7
1000
8
SELECT analog input channel 8
1001
9
SELECT analog input channel 9
1010
A
SELECT analog input channel 10
SELECT TEST,
1011
B
Voltage = (VREF+ + VREF–)/2
1100
C
SELECT TEST, Voltage = REFM
1101
D
SELECT TEST, Voltage = REFP
1110
E
SW POWERDOWN (analog + reference)
1111
F
Reserved
(1)
Select 12-bit output mode to achieve 200-KSPS sampling rate.
Copyright 2009, Texas Instruments Incorporated
21
Product Folder Link(s): TLV2553-Q1
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