参数资料
型号: TLV2553IDWRQ1
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封装: GREEN, PLASTIC, SOIC-20
文件页数: 16/28页
文件大小: 414K
代理商: TLV2553IDWRQ1
Reference
C1
0.1
F
Decoupling Cap
GND
Analog
Supply
Sample
50 pF
CDAC
Convert
REF+
REF
VCC
EOC Output
Chip-Select Input (CS)
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied
to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or
be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than
REF–.
Figure 39. Reference Block
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
Copyright 2009, Texas Instruments Incorporated
23
Product Folder Link(s): TLV2553-Q1
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TLV2556IDWRG4 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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