- 您现在的位置：买卖IC网 > PDF目录98252 > TLV320AIC22PT (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP48 PDF资料下载
参数资料
| 型号： | TLV320AIC22PT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | ROHS COMPLIANT, PLASTIC, LQFP-48 |
| 文件页数： | 25/55页 |
| 文件大小： | 782K |
| 代理商： | TLV320AIC22PT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页
TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ADC and DAC channel data (continued)
On the receive side (DAC), the DSP can use the same flag bits it extracts from the DOUT bit stream. It can use
it as the DATA request signal for the DAC of the same codec and send the DAC data on DIN during the next
frame.
The valid data appears in the Ith or (I + N)th frame. For every D number of valid ADC data bytes, the ADC
transmits a valid data word in the (I + 1)th frame, for N times, and in the Ith frame for (D – N) times. I, N, and
D are the values used for the (I + N/D) divider.
For this example where MCLK = 32.768 MHz, I + N/D = 4 + 4/9 and the sample rate is 14.4 kHz, the ADC data
will appear in the fifth frame four times and in the fourth frame five times, repeating. The valid data bit/FSYNC
pattern will be (in terms of frame syncs):
4, 5, 4, 5, 4, 5, 4, 5, 4
Then, this sequence repeats. See Table 12 for I, N, and D derivations for this example.
Table 12. I, N, and D Derivation for 32.768-MHz Clock and 14.4-kHz Sampling Rate
PARAMETER OR VARIABLE
EQUATION
VALUE
MCLK
None
32.768 MHz (given)
BCLK
MCLK/2
16.384 MHz
FSYNC
BCLK/256
64 kHz
Sample rate
MCLK/(512 x (I + N/D))
14.4 kHz (given)
I + N/D
MCLK/(512 x sample rate)
4.4444
I
4
N
4
D
9
Example 3: This example is for the case where codec 1 and codec 2 have different sampling rates. If an 8-kHz
sampling rate is needed on codec 1, then codec 1 sends a valid data word every eighth frame for its particular
time slot. If a 16-kHz sampling rate is needed on codec 2, then codec 2 sends a valid data word every fourth
frame for its particular time slot. Table 13 shows the derivation of the parameters for each codec. A 32.768-MHz
master clock is assumed.
Table 13. I, N, and D Derivation for 32.768-MHz Clock, With an 8-kHz Sampling Rate for
Codec 1 and a 16-kHz Sampling Rate for Codec 2
PARAMETER OR
VARIABLE
CODEC
EQUATION
VALUE
MCLK
–
None
32.768 MHz (given)
BCLK
–
MCLK/2
16.384 MHz
FSYNC
–
BCLK/256
64 kHz
Sample rate
Codec 1
MCLK/[512 x (I + N/D)]
8 kHz (given)
I + N/D
Codec 1
MCLK/(512 x sample rate)
8
I
Codec 1
8
N
Codec 1
0
D
Codec 1
9
Sample rate
Codec 2
MCLK/[512 x (I + N/D)]
16 kHz (given)
I + N/D
Codec 2
MCLK/(512 x sample rate)
4
I
Codec 2
4
N
Codec 2
0
D
Codec 2
9
相关PDF资料 |
PDF描述 |
|---|---|
| TLV320AIC22PTR | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TLV320AIC23BGQE | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| TLV320AIC23BIGQE | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| TLV320AIC23BIPW | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| TLV320AIC23BPW | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV320AIC22PTR | 功能描述:接口—CODEC DUAL VOIP CODEC RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC23 | 制造商:TI 制造商全称:Texas Instruments 功能描述:STereo Audio CODEC, 8- to 96kHz, With Integrated Headphone Amplifier |
| TLV320AIC23_06 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
| TLV320AIC23B | 制造商:TI 制造商全称:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
| TLV320AIC23B_06 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
发布紧急采购，3分钟左右您将得到回复。