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参数资料
| 型号： | TLV320AIC23BIPWRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | PLASTIC, TSSOP-28 |
| 文件页数： | 17/41页 |
| 文件大小： | 260K |
| 代理商： | TLV320AIC23BIPWRQ1 |
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37
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only
dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to the same
value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5
Analog Bypass Mode
The TLV320AIC23B includes a bypass mode in which the analog line inputs are directly routed to the analog line
outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control
register[see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone
output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and
microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater
than 1.0Vrms at AVDD=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AVDD.
3.2.6
Sidetone Insertion
The TLV320AIC23B has a sidetone insertion made where the microphone input is routed to the line and headphone
outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to
6 dB, 9 dB, 12 dB, 15 dB, or 0dB, by software selection (see Section 3.1.3). If this mode is used to sum the
microphone input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping
and distortion.
3.3
Digital Audio Interface
3.3.1
Digital Audio-Interface Modes
The TLV320AIC23B supports four audio-interface modes.
Right justified
Left justified
I2S mode
DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals
LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT
(see Figure 3-5).
LRCIN/
BCLK
DIN/
n
n1
0
1
n1
n
1/fs
Left Channel
Right Channel
1
0
MSB
LSB
LRCOUT
DOUT
Figure 35. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT
(see Figure 3-6)
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