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参数资料
| 型号： | TLV320AIC23BIPWRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | PLASTIC, TSSOP-28 |
| 文件页数： | 2/41页 |
| 文件大小： | 260K |
| 代理商： | TLV320AIC23BIPWRQ1 |
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15
1.5
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
PW
I/O
DESCRIPTION
AGND
15
Analog supply return
AVDD
14
Analog supply input. Voltage level is 3.3 V nominal.
BCLK
3
I/O
I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the DSP. In audio slave
mode, the signal is generated by the DSP.
BVDD
1
Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
CLKOUT
2
O
Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Bit 07 in
the sample rate control register controls frequency selection.
CS
21
I
Control port input latch/address select. For SPI control mode this input acts as the data latch control. For 2-wire
control mode this input defines the seventh bit in the device address field. See Section 3.1 for details.
DIN
4
I
I2S format serial data input to the sigma-delta stereo DAC
DGND
28
Digital supply return
DOUT
6
O
I2S format serial data output from the sigma-delta stereo ADC
DVDD
27
Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND
11
Analog headphone amplifier supply return
HPVDD
8
Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
LHPOUT
9
O
Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of –73 dB to
6 dB is provided in 1-dB steps.
LLINEIN
20
I
Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB
steps.
LOUT
12
O
Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
LRCIN
5
I/O
I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the
DSP. In audio slave mode, the signal is generated by the DSP.
LRCOUT
7
I/O
I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the
DSP. In audio slave mode, the signal is generated by the DSP.
MICBIAS
17
O
Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4 AVDD
nominal.
MICIN
18
I
Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a default
gain of 5 is provided. See Section 2.3.1.2 for details.
MODE
22
I
Serial-interface-mode input. See Section 3.1 for details.
NC
Not Used—No internal connection
RHPOUT
10
O
Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of 73 dB to
6 dB is provided in 1-dB steps.
RLINEIN
19
I
Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB
steps.
ROUT
13
O
Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
SCLK
24
I
Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See Section 3.1 for
details.
SDIN
23
I
Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is used to
select the control protocol after reset. See Section 3.1 for details.
VMID
16
I
Midrail voltage decoupling input. 10-
F and 0.1-F capacitors should be connected in parallel to this terminal for
noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK
25
I
Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
XTO
26
O
Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing master. Not used
in applications where external clock source is used.
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