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参数资料
| 型号： | TLV320AIC26IRHBRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 16/67页 |
| 文件大小： | 883K |
| 代理商： | TLV320AIC26IRHBRG4 |
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TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
23
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable coefficients (one
set per channel). The filter is implemented as cascade of two biquad sections with frequency response given by:
N0
) 2
N1
z*1
) N2
z*2
32768
* 2
D1
z*1
* D2
z*2
N3
) 2
N4
z*1
) N5
z*2
32768
* 2
D4
z*1
* D5
z*2
The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed depending on bit D1 of
register 05H/Page2. The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being
the most commonly used in portable audio applications. The default N and D coefficients in the part are given by:
N0 = N3 = 27619
D1 = D4 = 32131
N1 = N4 = 27034
D2 = D5 = 31506
N2 = N5 = 26461
and implement a shelving filter with 0 dB gain from dc to approximately 150 Hz, at which point it rolls off to a 3-dB attenuation
for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented
by 16-bit twos complement numbers with values ranging from –32768 to +32767. Frequency response plots are given in
the Audio Codec Filter Frequency Responses section of this data sheet.
Interpolation Filter
The interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio. It
provides a linear phase output with a group delay of 21/Fs.
In addition, a digital interpolation filter provides enhanced image filtering and reduces signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples
of 8 kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc). The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener;
therefore, they must be filtered heavily to maintain good output quality. The interpolation filter is designed to maintain at
least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the programmable interpolation capability, the
Fsref should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use),
and the actual Fs is set using the dividers in bit D5D3/REG00H/Page2. For example, if Fs = 8 kHz is required, then Fsref
can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the 8-kHz data are sufficiently attenuated
well beyond the ~20-kHz audible frequency range.
Delta-Sigma DAC
The audio digital-to-analog converter incorporates a third order multibit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping
techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter followed by a continuous time RC
filter. The analog FIR operates at a rate of 128 x Fsref (6.144 MHz when Fsref = 48 kHz, 5.6448 MHz when Fsref = 44.1 kHz).
Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must
be taken to keep jitter on this clock to a minimum.
DAC Digital Volume Control
The DAC has a digital volume control block, which implements programmable gain. The volume level can be varied from
0 dB to –63.5 dB in 0.5 dB steps. In addition, there is an independent mute bit for each channel. The volume level of both
channels can also be changed simultaneously by the master volume control. The gain is implemented with a soft-stepping
algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume
is reached. The rate of soft-stepping can be slowed to one step per two input samples through bit D1 of control register
04H/Page2.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the
host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this
situation, the ’AIC26 provides a flag back to the host via a read-only register bit (D2D3 of control register 04H/Page2) that
alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level.
The soft-stepping feature can be disabled by programming D14=1 in register 1DH in Page02. If soft-stepping is enabled,
the MCLK signal to the device should not be changed until the DAC power-down flag is set. When this flag is set, the internal
soft-stepping process and power-down sequence is complete, and the MCLK can be stopped if desired.
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