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参数资料
| 型号： | TLV320AIC26IRHBRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 8/67页 |
| 文件大小： | 883K |
| 代理商： | TLV320AIC26IRHBRG4 |
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TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
16
OPERATIONAUDIO CODEC
Audio Analog I/O
The ’AIC26 has one mono audio input (MICIN) typically used for microphone recording, and an auxiliary input (AUX) that
can be used as a second microphone or line input. The dual audio output drivers have programmable power level and can
be configured to drive up to 325 mW into an 8-
speaker, or to drive 16- stereo headphones at over 30-mW per channel,
or to provide a stereo line-level output. The power level of the output drivers is controlled using bit D12 in control register
REG05H/Page2. The ’AIC26 also has a virtual ground (VGND) output driver, which can optionally be used to connect
the return terminal of headphones, to eliminate the ac-coupling capacitors needed at the headphone output. The VGND
amplifier is controlled by bit D8 of REG05H/Page2. A special circuit has also been included in the ’AIC26 to insert a short
keyclick sound into the stereo audio output, even when the audio DAC is powered down. The keyclick sound is used to
provide feedback to the user when a particular button is pressed or item is selected. The specific sound of the keyclick can
be adjusted by varying several register bits that control its frequency, duration, and amplitude.
Audio Digital Interface
Digital audio data samples are transmitted between the ’AIC26 and the audio processor via the serial bus (BCLK, ADWS,
DOUT, LRCK, DIN) that can be configured to transfer digital data in four different formats: right justified, left justified, I2S,
and DSP. The four modes are MSB-first and operate with variable word length of 16, 20, 24, or 32 bits. The digital audio
serial bus of the ’AIC26 can operate in master or slave mode, depending on its register settings. The word-select signals
(ADWS, LRCK) and bit clock signal (BCLK) are configured as outputs when the bus is in master mode. They are configured
as inputs when the bus is in slave mode. The ADWS is representative of the sampling rate of the audio ADC and is
synchronized with DOUT. The LRCK is representative of the audio DAC sampling rate and is synchronized with DIN.
Although the DOUT signal can contain two channels of information (a left and right channel), the ’AIC26 sends the same
ADC data in both channels.
D ADC/DAC SAMPLING RATE
The Audio Control 1 register (Register 00H, Page2) determines the sampling rates of the audio DAC and ADC, which
are scaled down from a reference rate (Fsref). The ADC and DAC can operate with either a common LRCK (equal
sampling rates) or separate ADWS and LRCK (unequal sampling rates). When the audio codec is powered up, it is
configured by default as an I2S slave with both the DAC and ADC operating at Fsref.
D WORD SELECT SIGNALS
The word select signal (LRCK, ADWS) indicates the channel being transmitted:
LRCK/ADWS = 0: left channel for I2S mode
LRCK/ADWS = 1: right channel for I2S mode
For other modes see the timing diagrams below.
Bitclock (BCLK) Signal
In addition to flexibility as master or slave mode, the BCLK can also be configured in two transfer modes—256S and
Continuous Transfer Modes. These modes are set using bit D12/REG06h/Page2.
D 256S TRANSFER MODE
In the 256S mode, the BCLK rate always equals 256 times the maximum of the LRCK and ADWS frequencies. In
the 256S mode, the combination of ADC/DAC sampling rate equal to Fsref (as selected by bit
D5D0/REG00h/Page2) and leftjustified mode is not supported.
D CONTINUOUS TRANSFER MODE
In the continuous transfer mode, the BCLK rate always equals two times the word length of the maximum of the LRCK
and ADWS frequencies.
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