参数资料
型号: TLV5618ACDG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8
封装: GREEN, PLASTIC, SOIC-8
文件页数: 20/23页
文件大小: 633K
代理商: TLV5618ACDG4
TLV5618A
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230H – JULY 1999 – REVISED JULY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
digital input timing requirements
MIN
NOM
MAX
UNIT
C and I suffixes
VDD = 5 V
5
ns
tsu(CS-CK)
Setup time, CS low before first negative SCLK edge
C and I suffixes
VDD = 3 V
10
ns
tsu(CS-CK)
Setu time, CS low before first negative SCLK edge
Q and M suffixes
10
ns
tsu(C16-CS)
Setup time, 16th negative SCLK edge before CS rising edge
10
ns
tw(H)
SCLK pulse width high
25
ns
tw(L)
SCLK pulse width low
25
ns
C and I suffixes
VDD = 5 V
5
tsu(D)
Setup time, data ready before SCLK falling edge
C and I suffixes
VDD = 3 V
10
ns
tsu(D)
Setu time, data ready before SCLK falling edge
Q and M suffixes
8
ns
C and I suffixes
VDD = 5 V
5
th(D)
Hold time, data held valid after SCLK falling edge
C and I suffixes
VDD = 3 V
10
ns
h(D)
gg
Q and M suffixes
10
th(CSH)
Hold time CS high between cycles
VDD = 5 V
25
ns
th(CSH)
Hold time, CS high between cycles
VDD = 3 V
50
ns
timing requirements
tw(L)
SCLK
CS
DIN
D15
D14
D13
D12
D1
D0
X
1
X
2
3
4
5 15
16
X
tw(H)
tsu(D) th(D)
tsu(CS-CK)
tsu(C16-CS)
Figure 1. Timing Diagram
相关PDF资料
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