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参数资料
型号： TLV5618AQD
厂商： TEXAS INSTRUMENTS INC
元件分类： DAC
英文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO8
封装： PLASTIC, SOIC-8
文件页数： 19/23页
文件大小： 633K
代理商： TLV5618AQD
TLV5618A
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS230H – JULY 1999 – REVISED JULY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
reference input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
0
VDD–1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference input bandwidth
REF=0 2V
+1 024Vdc
Fast
1.3
MHz
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Slow
525
kHz
Reference feedthrough
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
– 80
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = VDD
1
A
IIL
Low-level digital input current
VI = 0 V
–1
A
Ci
Input capacitance
8
pF
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Output settling time full scale
R10 k
C
100 pF See Note 11
Fast
1
3
s
ts(FS)
Output settling time, full scale
RL = 10 k,CL = 100 pF, See Note 11
Slow
3
10
s
t
Output settling time code to code
R10 k
C
100 pF See Note 12
Fast
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,CL = 100 pF, See Note 12
Slow
2
s
SR
Slew rate
R10 k
C
100 pF See Note 13
Fast
3
V/ s
SR
Slew rate
RL = 10 k,CL = 100 pF, See Note 13
Slow
0.5
V/
s
Glitch energy
DIN = 0 to 1,
FCLK = 100 kHz, CS = VDD
5
nV–s
SNR
Signal-to-noise ratio
76
SINAD
Signal-to-noise + distortion
fs = 102 kSPS, fout = 1 kHz, RL = 10 k,
68
dB
THD
Total harmonic distortion
fs = 102 kSPS, fout = 1 kHz, RL = 10 k,
CL = 100 pF
–68
dB
SFDR
Spurious free dynamic range
L
72
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
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