参数资料
型号: TLV5624IDGK
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 8-BIT DAC, PDSO8
封装: GREEN, PLASTIC, MSOP-8
文件页数: 19/22页
文件大小: 571K
代理商: TLV5624IDGK
TLV5624
2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235B JULY 1999 REVISED APRIL 2004
6
WWW.TI.COM
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CSFS)
Setup time, CS low before FS falling edge
10
ns
tsu(FS-CK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16-FS)
Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16-CS)
Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of 16th positive edge to update DAC, then setup time between
FS rising edge and CS rising edge.
10
ns
twH
SCLK pulse duration high
25
ns
twL
SCLK pulse duration low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
tH(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
FS pulse duration high
25
ns
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
CS
DIN
FS
D15
D14
D13
D12
D1
D0
X
1
X
2
3
4
5 15
16
X
twH
tsu(D) th(D)
tsu(CS-FS)
twH(FS)
tsu(FS-CK)
tsu(C16-FS)
tsu(C16-CS)
Figure 1. Timing Diagram
相关PDF资料
PDF描述
TLV5624CDRG4 SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 8-BIT DAC, PDSO8
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TLV5625IDRG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8
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