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参数资料
| 型号： | TLV5636IDGKG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封装： | GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 17/23页 |
| 文件大小： | 521K |
| 代理商： | TLV5636IDGKG4 |
www.ti.com
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TLV5636
SLAS223C – JUNE 1999 – REVISED APRIL 2004
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Supply voltage (VDD to AGND)
7 V
Reference input voltage
- 0.3 V to VDD + 0.3 V
Digital input voltage range
- 0.3 V to VDD + 0.3 V
TLV5636C
0°C to 70°C
Operating free-air temperature range, TA
TLV5636I
-40°C to 85°C
Storage temperature range, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN
NOM
MAX
UNIT
VDD = 5 V
4.5
5
5.5
V
Supply voltage, VDD
VDD = 3 V
2.7
3
3.3
V
Power on Reset, POR
0.55
2
V
DVDD = 2.7 V
2
High-level digital input voltage, VIH
V
DVDD = 5.5 V
2.4
DVDD = 2.7 V
0.6
Low-level digital input voltage, VIL
V
DVDD = 5.5 V
1
VDD = 5 V(1)
AGND
2.048
VDD - 1.5
V
Reference voltage, Vref to REF terminal
VDD = 3 V(1)
AGND
1.024
VDD - 1.5
V
Load resistance, RL
2
k
Load capacitance, CL
100
pF
Clock frequency, fCLK
20
MHz
TLV5636C
0
70
Operating free-air temperature, TA
°C
TLV5636I
-40
85
(1)
Due to the x2 output buffer, a reference input voltage . (VDD - 0.4 V)/2 causes clipping of the transfer function. The output buffer of the
internal reference must be disabled, if an external reference is used.
over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
POWER SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No load,
Fast
2.3
3.3
IDD
Power supply current
All inputs = AGND or VDD,
mA
Slow
1.5
1.9
DAC latch = 0x800
Power-down supply current
See Figure 8
0.01
10
A
Zero scale (1)
-65
PSRR
Power supply rejection ratio
dB
Full Scale(2)
-65
(1)
Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax]
(2)
Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax]
3
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